Method and circuit for generating constant slew rate output signal
AssigneeMicron Technology, Inc.
InventorDong Pan
Life of this patent
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Abstract
An improved output buffer having a substantially constant slew rate comprises a slew rate control circuit and an output driver circuit. The slew rate control circuit is configured at the input terminals of the output driver circuit to suitably control the slew rate of the input signal for the output driver circuit based on the level of voltage of a power supply for the output driver circuit. For increases in the voltage of the power supply, the slew rate of the input signal of the output driver circuit is decreased, while for decreases in the voltage of the power supply, the slew rate of the input signal of the output driver circuit is increased, such that the variation of the slew rate of the output signal of the output buffer is significantly reduced.
Claims44
An output buffer configured for use within DRAM applications, said output buffer comprising:
- a predriver circuit configured for providing a drive input signal;
- an output driver circuit configured for providing an output signal for said output buffer, said output driver circuit coupled to a power supply;
- and
- a slew rate control circuit coupled between said predriver circuit and said output driver circuit and configured for controlling a slew rate of said drive input signal based on a level of voltage in said power supply provided to said output driver circuit.
An output buffer configured for use within DRAM applications, said output buffer comprising:
- a predriver circuit configured for providing a drive input signal;
- an output driver circuit configured for providing an output signal for said output buffer, wherein said output driver circuit comprises:
- a pull-up transistor having a source terminal configured for coupling to the power supply, and a gate terminal coupled to said slew rate control circuit;
- and
- a pull-down transistor having a source terminal configured for coupling to a ground connection, a drain terminal coupled to a drain terminal of said pull-up transistor, and a gate terminal coupled to said slew rate control circuit;
- and
- a slew rate control circuit coupled between said predriver circuit and said output driver circuit and configured for controlling a slew rate of said drive input signal based on a level of voltage in a power supply provided to said output driver circuit.
An output buffer configured for use within DRAM applications, said output buffer comprising:
- a predriver circuit configured for providing a drive input signal;
- an output driver circuit configured for providing an output signal for said output buffer, and
- a slew rate control circuit coupled between said predriver circuit and said output driver circuit and configured for controlling a slew rate of said drive input signal based on a level of voltage in a power supply provided to said output driver circuit, wherein said slew rate control circuit comprises:
- a first amplifier circuit configured for controlling a slew rate of a pull-up input signal and providing said controlled pull-up input signal to said output driver circuit;
- and
- a second amplifier circuit configured for controlling a slew rate of a pull-down input signal and providing said controlled pull-down input signal to said output driver circuit.
A slew rate control circuit for controlling the slew rate of an output signal of an output buffer, said slew rate control circuit comprising:
- a first amplifier circuit for receiving a first input drive signal and controlling a slew rate of said first input drive signal based on changes in voltage of a power supply coupled to the output buffer;
- a first current source coupled to said first amplifier circuit, said first current source configured for providing a first biasing current to said first amplifier circuit to facilitate control of said slew rate of said first input drive signal;
- a second amplifier circuit for receiving a second input drive signal and controlling a slew rate in said second input drive signal based on changes in voltage of the power supply coupled to the output buffer;
- and
- a second current source coupled to said second amplifier circuit, said second current source configured for providing a second biasing current to said second amplifier circuit to facilitate control of said slew rate of said second input drive signal.
A method for slew rate regulation of an output signal in an output buffer, said method comprising the steps of:
- receiving in a slew rate control circuit an input drive signal from a predriver circuit;
- determining a level of voltage of a power supply for said output buffer;
- and
- controlling said slew rate of said output signal through adjustment of a slew rate of said input drive signal based on said level of voltage of the power supply.
A method for slew rate regulation of an output signal in an output buffer, said method comprising the steps of:
- receiving in a slew rate control circuit an input drive signal from a predriver circuit;
- determining a level of voltage of a power supply for said output buffer;
- comparing said level of voltage of said power supply with a reference voltage;
- and
- controlling said slew rate of said output signal through adjustment of a slew rate of said input drive signal based on said level of voltage of the power supply.
A method for slew rate regulation of an output signal in an output buffer, said method comprising the steps of:
- receiving in a slew rate control circuit an input drive signal from a predriver circuit;
- determining a level of voltage of a power supply for said output buffer;
- controlling said slew rate of said output signal through adjustment of a slew rate of said input drive signal based on said level of voltage of the power supply, wherein said step of controlling said slew rate of said output signal comprises at least one of the steps of:
- increasing a bias current in an amplifier circuit of said slew rate control circuit when said level of voltage of the power supply is less than a reference voltage;
- and
- decreasing a bias current in an amplifier circuit of said slew rate control circuit when said level of voltage of the power supply is greater than a reference voltage.
An DRAM output buffer comprising:
- a predriver circuit configured for providing a pull-up input signal and a pull-down input signal;
- an output driver circuit configured for providing an output signal;
- and
- a slew rate control circuit configured for controlling a slew rate of said pull-up input signal and said pull-down input signal based on levels of voltage of a power supply coupled to said output driver circuit, and configured for providing a controlled pull-up signal and a controlled pull-down signal to said output driver circuit.
A memory system having an output buffer configured for providing an operating voltage to a memory device, said output buffer comprising:
- an output driver circuit configured for providing an output signal, said output driver circuit coupled to a power supply;
- and
- a slew rate control circuit configured for receiving input control signals and for providing controlled drive signals to said output driver circuit, said slew rate control circuit configured for controlling a slew rate of said controlled drive signals based on voltage changes in said power supply coupled to said output driver circuit.
An electronic system comprising a processor, a supply and a memory system, said memory system having an output buffer comprising:
- a predriver circuit configured for providing an input signal for controlling said output buffer;
- an output driver circuit configured for providing an output signal for said output buffer, said output driver circuit coupled to a power supply;
- and
- a slew rate control circuit coupled to said predriver circuit to receive said input signal and to provide a controlled drive signal to said output driver circuit, said slew rate control circuit configured for controlling a slew rate for said controlled drive signal based on voltage level in said power supply coupled to said output driver circuit.
A slew rate control circuit for controlling the slew rate of an output signal of an output buffer, said slew rate control circuit comprising:
- an amplifier circuit for receiving an input drive signal and controlling a slew rate of said input drive signal based on a level of voltage of a power supply coupled to the output buffer;
- and
- a current source coupled to said amplifier circuit, said current source configured for providing a biasing current to said amplifier circuit to facilitate control of said slew rate of said input drive signal;
- and
- wherein said slew rate control circuit is configured to control any increases and decreases in the slew rate of the output signal of the output buffer through decreases and increases in said biasing current.
Dependencies are inferred from the claim text.