US 6,714,461 B2 · Semiconductor device with data output circuit having slew rate adjustable

Abstract

Data for switching a slew rate of a data output circuit included in a data input/output circuit between a slew rate in a normal mode and a slow slew rate is stored in a mode register. According to the data stored in mode register, a slew rate setting signal is generated. According to a slew rate switching circuit, the slew rate of the data input/output circuit is switched between a slew rate in the normal mode and a slow slew rate slower than the slew rate in the normal mode. A data output circuit is achieved which occupies a small area, is capable of setting a slew rate slower than the slew rate in a normal mode and outputting data without causing an erroneous operation with a low consumption current even when the slew rate is adjusted.

Claims13

Dependent claims

A semiconductor device comprising:

a plurality of transistors connected in parallel to an output node;
a register circuit for storing data for setting an operation state of each of said transistors, said register circuit storing either of a default value for designating a driving capability of said output node in a normal mode and slow slew rate data for designating a driving capability of said output node smaller than said default value;
and
an output driving circuit for driving said plurality of transistors in accordance with an internal signal, said output driving circuit selectively driving said plurality of transistors in accordance with said internal signal based on data stored in said register circuit.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

10/139,751Filed 7 May 2002

Priority

JP 2001-17703412 Jun 2001

Published

US 2002/0186596 A112 Dec 2002

Granted

30 Mar 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
G11C 7/1045
Read-write modes for single port memories, i.e. having either a random port or a serial port: read-write mode select circuits
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…

Semiconductor device with data output circuit having slew rate adjustable

Life of this patent

Semiconductor device with data output circuit having slew rate adjustable

Life of this patent

Abstract

Claims13