System and method for multiplexing data and data masking information on a data bus of a memory device
AssigneeMicron Technology, Inc.
InventorPaul A. LaBerge
Life of this patent
Estimating the term…
Abstract
A method and system masking data being written to a memory device having a data bus. One method includes applying masking data on the data bus, storing the masking data in the memory device, applying write data on the data bus, storing the write data in the memory device, and applying the stored masking data to mask the stored write data.
Claims53
A method of masking data being written to a memory device, the memory device including a data bus, the method comprising:
- applying masking data on the data bus;
- storing the masking data in the memory device;
- applying as write data a burst of data words sequentially applied on the data bus;
- storing the write data in the memory device;
- and
- applying the stored masking data to mask the stored write data.
A method of transferring masking data to a memory device having a data bus, the method comprising applying masking data on the data bus, storing the masking data in the memory device, and applying as write data a burst of data words sequentially applied on the data bus, the stored masking data for masking the write data.
A method of masking data being transferred to a memory device, the memory device including a data bus, and the method comprising:
- applying a sequence of data words on the data bus;
- storing the sequence of data words in the memory device;
- identifying at least one of the data words as being a data word containing masking data;
- and
- applying the masking data in each identified data word to mask the data in the other data words.
A method of masking data being written to a memory device, the memory device including data, control, and address busses, and the method comprising:
- applying a write partial command to the memory device over the control and address busses;
- applying a sequence of data words on the data bus;
- storing the sequence of data words in the memory device;
- decoding the applied write partial command;
- in response to the decoded write partial command,
- identifying at least one of the data words as being a data word containing masking data;
- applying the masking data in each identified data word to mask the data in the other data words;
- and
- storing the masked data in addressed memory cells in the memory device.
A read/write circuit adapted to receive data words and data masking words applied on a data bus and adapted to receive read data from a memory-cell array, the read/write circuit operable during a read mode to apply read data received from the array on the data bus, and operable during a write-partial mode to store at least one data masking word and at least one data word applied on the data bus, and operable to apply each data masking word to mask each data word and to thereafter apply each masked data word to the memory-cell array.
A read/write circuit adapted to receive data words and data masking words applied on a data bus and adapted to receive read data from a memory-cell array, the read/write circuit operable during a read mode to apply read data received from the array on the data bus, and operable during a write mode to store data words applied on the data bus and apply the data words to the memory-cell array, and operable during a write-partial mode to store at least one data masking word and at least one data word applied on the data bus, and operable to apply masking data contained in each data masking word to selectively mask and not mask data contained in each data word, and to thereafter apply the masked and not masked data to the memory-cell array.
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder and control circuit;
- a read/write circuit coupled to the data bus and the memory-cell array, the read/write circuit operable during a read mode to apply read data received from the memory-cell array on the data bus, and operable during a write-partial mode to receive at least one data masking word and at least one data word applied on the data bus and store the received words, and operable to apply each data masking word to mask each data word and to thereafter apply each masked data word to the memory-cell array.
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder and control circuit;
- a read/write circuit coupled to the data bus and the memory-cell array, the read/write circuit operable during a read mode to apply read data received from the memory-cell array on the data bus, and operable during a write-partial mode to receive at least one data masking word and at least one data word applied on the data bus and store the received words, and operable to apply each data masking word to mask each data word and to thereafter apply each masked data word to the memory-cell array.
Dependencies are inferred from the claim text.