High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices
AssigneeMicron Technology, Inc.
InventorsStephen J. Gualandri, Theodore T. Pekny
Life of this patent
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Abstract
An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.
Claims42
A voltage discharge circuit coupled to a first node and a second node and receiving first and second discharge signals, the voltage discharge circuit operable in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate, and operable in a second mode in response to the second discharge signal to discharge the voltages on the first and second nodes at a second rate.
An erase discharge circuit, comprising:
- a first switching circuit coupled between the array source and p-well drive and receiving a first discharge signal, the first switching circuit operable to couple the array source to the p-well responsive to the first discharge signal;
- a second switching circuit receiving the first discharge signal and coupled between the array source and p-well drive and ground, the second switching circuit operable in response to the first discharge signal to control the flow of current from the array source and p-well drive to ground;
- and
- a third switching circuit receiving a second discharge signal and coupled between the array source and p-well drive and ground, the third switching circuit operable in response to the second discharge signal to couple the array source and p-well drive to ground.
An erase discharge circuit, comprising:
- a control circuit adapted to receive a first discharge signal and a second discharge signal and operable in a first mode responsive to the first discharge signal being active to develop a first activation signal and to control a rate of increase of a magnitude of the first activation signal, and operable in a second mode responsive to the second discharge signal being active to develop a second activation signal and to control a rate of increase of a magnitude of the second activation signal;
- a first switching circuit coupled between the array source and p-well drive and coupled to the control circuit to receive the first activation signal, the first switching circuit operable to present an impedance having a value that is a function of the magnitude of the first activation signal;
- a current-limiting device having a first node coupled to ground and having a second node, the current limiting device allowing a current to flow from the second node to the first node;
- a second switching circuit coupled between the array source and p-well drive and the second node of the current-limiting device, and being coupled to the control circuit to receive the first activation signal, the second switching circuit operable to present an impedance having a value that is a function of the magnitude of the first activation signal to discharge the array source and p-well drive at a first rate, the first rate having a value that is a function of the current through the current-limiting device and the impedance of the second switching circuit;
- and
- a third switching circuit coupled to the control circuit to receive the second discharge signal and coupled to the first and second nodes of the current-limiting device, the third switching circuit operable in response to the second discharge signal to couple the second node to ground to discharge the array source and p-well drive at a second rate.
An erase discharge circuit coupled to the array source and p-well drive of a block of memory cells and receiving first and second discharge signals, the erase discharge circuit operable in a first mode in response to the first discharge signal to couple the array source to the p-well drive and to discharge current from the array source and p-well drive at a first rate until the voltages on the array source and p-well drive are within a threshold value of a reference voltage, the threshold value being substantially less than an initial value of the voltages on the array source and p-well drive, and the erase discharge circuit operable in a second mode in response to the second discharge signal to discharge current from the array source and p-well drive at a second rate until voltages on the array source and p-well drive are approximately equal to the reference voltage.
An erase discharge circuit coupled to the array source and p-well drive of a block of memory cells and receiving first and second discharge signals, the erase discharge circuit operable in a first mode in response to the first discharge signal to couple the array source to the p-well drive and to discharge current from the array source and p-well drive for a first time period until the voltages on the array source and p-well drive are within a threshold value of a reference voltage, the threshold value being substantially less than an initial value of the voltages on the array source and p-well drive, and the erase discharge circuit operable in a second mode in response to the second discharge signal to discharge current from the array source and p-well drive for a second time period until voltages on the array source and p-well drive are substantially equal to the reference voltage.
A flash memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a flash memory-cell array coupled to the address decoder, control circuit, and read/write circuit, and including an array source and p-well drive;
- and
- an erase discharge circuit coupled to the array source and p-well drive and coupled to the control circuit to receive first and second discharge signals, the erase discharge circuit operable in a first mode in response to the first discharge signal to couple the array source to the p-well drive and to discharge voltages on the array source and p-well drive at a first rate, and operable in a second mode in response to the second discharge signal to couple the array source to the p-well drive and to discharge the voltages on the array source and p-well drive at a second rate.
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a flash memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a flash memory-cell array coupled to the address decoder, control circuit, and read/write circuit, and including an array source and p-well drive;
- and
- an erase discharge circuit coupled to the array source and p-well drive and coupled to the control circuit to receive first and second discharge signals, the erase discharge circuit operable in a first mode in response to the first discharge signal to couple the array source to the p-well drive and to discharge voltages on the array source and p-well drive at a first rate, and operable in a second mode in response to the second discharge signal to couple the array source to the p-well drive and to discharge the voltages on the array source and p-well drive at a second rate.
A method of discharging first and second voltages on first and second nodes, respectively, the method comprising:
- coupling the first node to the second node;
- discharging the voltages on the first and second nodes at a first rate;
- and
- discharging the first and second voltages at a second rate.
A method of discharging first, second, and third voltages on first, second, and third nodes, respectively, the first and second nodes being electrically coupled to the third node, the method comprising:
- coupling the first node to the second node;
- discharging current from the third node;
- discharging current from the first and second nodes;
- controlling a rate of the discharge of current from the first and second nodes, the rate being controlled to reduce an influence of the discharge of current from the first and second nodes on the voltage on the third node;
- and
- discharging current from the first and second nodes at a second rate.
Dependencies are inferred from the claim text.