US 6,714,457 B1 · Parallel channel programming scheme for MLC flash memory

Abstract

In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.

Claims36

Dependent claims

A method of parallel programming flash multiple level cell (MLC) memory comprising

a) coupling a plurality of voltages simultaneously to both the bit line and the source line of a plurality of memory cells for a predetermined amount of time,
b) coupling a high word line voltage to a word line connecting to said plurality of memory cells for said predetermined amount of time,
c) programming said plurality of memory cells to a plurality of threshold voltages wherein said threshold voltage of said memory cell coupled to a larger bit line voltage is smaller than said threshold voltage of said memory cell coupled to a smaller bit line voltage,
d) verifying the programming of said N memory cells.

1 more element

A method of parallel programming four flash memory multiple level cells (MLC) comprising:

a) coupling a first voltage to both a bit line and a source line of a first memory cell,
b) coupling a second voltage larger than said first voltage to both the bit line and the source line of a second memory cell,
c) coupling a third voltage larger than said second voltage to both the bit line and the source line of a third memory cell,
d) coupling a fourth voltage larger than said third voltage to both the bit line and the source line of a fourth memory cell,
e) coupling a word line voltage of high value to a word line coupled to control gates of said first, second, third and fourth memory cells,
f) programming said first memory cell to a first threshold voltage level, said second memory cell to a second threshold voltage level which is smaller than said first threshold voltage level, said third memory cell to a third threshold voltage level which is smaller than said second threshold voltage level, and said fourth memory cell to a fourth threshold voltage level which is smaller than said third threshold voltage level,
g) verifying said first memory cell is programmed to said first threshold voltage level, said second memory cell is programmed to said second threshold voltage level, said third memory cell is programmed to said third threshold voltage level, and said forth memory cell is programmed to said fourth threshold voltage level.

4 more elements

Dependencies are inferred from the claim text.

Parallel channel programming scheme for MLC flash memory

Life of this patent

Parallel channel programming scheme for MLC flash memory

Life of this patent

Abstract

Claims36