Semiconductor memory device including bit select circuit
AssigneeRenesas Technology Corp.
InventorsTsukasa Ooishi, Hiroshi Kato
Life of this patent
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Abstract
A plurality of nonvolatile memory cells having gates connected to a same word line, respectively, are connected in series, and connected to adjacent bit lines, respectively. When data is sequentially written to the plurality of nonvolatile memory cells, a bit line select circuit sequentially supplies a write potential outputted from a predetermined potential generation circuit to a plurality of bit lines. The bit line to which the write potential has been supplied once is kept to have the potential. Due to this, this nonvolatile semiconductor memory device can reduce an area occupied by a memory cell array.
Claims16
A nonvolatile semiconductor memory device comprising:
- a plurality of word lines arranged in rows;
- a plurality of bit lines arranged in columns;
- a plurality of nonvolatile memory cells arranged in the rows and the columns;
- a plurality of latch circuits arranged to be electrically connected to said plurality of bit lines, and latching a plurality of data inputted externally;
- and
- a bit line select circuit supplying a predetermined potential to said plurality of bit lines, respectively, and maintaining potentials on said plurality of bit lines supplied with the predetermined potential, wherein
- a plurality of nonvolatile memory cells arranged in each of said rows are connected in series, and gates thereof are connected to the word line arranged in the row, and
- said plurality of bit lines are connected with the plurality of nonvolatile memory cells arranged in two columns neighboring to each other, respectively.
A semiconductor memory device comprising:
- a memory cell array including a plurality of word lines arranged in rows, a plurality of bit lines arranged in columns, and a plurality of memory cells arranged in the rows and the columns;
- and
- a select circuit selecting one of said plurality of memory cells, wherein
- in said memory cell array, a plurality of memory cells arranged in each of the rows are connected in series, gates thereof are connected to the word line arranged in the row thereof, each of said plurality of bit lines is connected to a plurality of memory cells arranged in two columns neighboring each other, and said select circuit first selects the memory cell located at an end of said memory cell array, and each of said plurality of memory cells includes a plurality of storage sections, each storage section storing data.
A semiconductor memory device comprising:
- a plurality of normal memory cells;
- a spare memory cell;
- and
- a redundancy circuit determining which of said plurality of normal memory cells and said spare memory cell stores each of a plurality of pieces of data inputted externally, controlling a write operation, reading the data stored in said spare memory cell, and then determining which of the data stored in said plurality of normal memory cells and the data stored in said spare memory cell is outputted.
Dependencies are inferred from the claim text.