Word programmable EEPROM memory comprising column selection latches with two functions
AssigneeSTMicroelectronics S.r.l.
InventorsBertrand Bertrand, Mohamad Chehadi, David Naura
Life of this patent
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Abstract
An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.
Claims29
An electrically erasable and programmable memory comprising:
- an array of memory cells arranged in rows and columns;
- word lines connected to the rows of said array of memory cells;
- bit lines connected to the columns of said array of memory cells;
- a plurality of bit line selection transistors connected to said bit lines and being driven by bit line selection signals;
- a column decoder for providing a plurality of column selection signals;
- and
- a plurality of column selection latches connected to said column decoder for receiving respective column selection signals, each column selection latch for delivering a gate control signal applied to memory cells of a respective column, and comprising
- a locking element for receiving the respective column selection signal,
- a switch connected to said locking element for setting a value of the gate control signal based upon an output of the locking element, the gate control signal being equal to an erasing high voltage during erasing periods of the memory cells, and
- a bit line selection element for delivering a respective bit line selection signal having a value based upon an output of said locking element during programming and reading periods of the memory cells of the respective column, the bit line selection signal being substantially equal to the erasing high voltage during the erasing periods of the memory cells.
An electrically erasable and programmable memory comprising:
- an array of memory cells arranged in rows and columns;
- word lines connected to the rows of said array of memory cells;
- bit lines connected to the columns of said array of memory cells;
- a plurality of bit line selection transistors connected to said bit lines and being driven by bit line selection signals;
- a plurality of programming latches;
- a plurality of insulating transistors connected between said bit lines and said plurality of programming latches;
- a column decoder for providing a plurality of column selection signals;
- and
- a plurality of column selection latches connected to said column decoder for receiving respective column selection signals, each column selection latch for delivering a gate control signal applied to memory cells of a respective column, and for delivering a respective bit line selection signal.
A method of selecting bit lines in an electrically erasable and programmable memory comprising an array of memory cells arranged in rows and columns, word lines connected to the rows, and bit lines connected to the columns of the array of memory cells, a plurality of bit line selection transistors connected to the bit lines, a column decoder, and a plurality of column selection latches connected to the column decoder, each column selection latch comprising a locking element and a conductive path connected to an output of the locking element, the method comprising:
- delivering a column selection signal from the column decoder to a selected column selection latch and storing the column selection signal in the locking element associated therewith;
- delivering a gate control signal from the selected column selection latch to memory cells of a respective column;
- and
- delivering a bit line selection signal from the conductive path connected to the output of the locking element associated with the selected column selection latch to bit lines of the respective column.
Dependencies are inferred from the claim text.