Method of programming a multi-level memory device

A method of programming a multi-level memory device comprising:

• connecting a plurality of memory cells to a wordline in a memory array of the multi-level memory device, each of the plurality of memory cells also being connected to a respective I/O control circuit;
• providing a plurality of signal lines, including a first and a second signal line, each of the plurality of signal lines being connected between the I/O control circuits and a memory controller of the memory device;
• applying a plurality of programming pulses to a set of the plurality of memory cells to place an amount of charge on a floating gate of each of said memory cell, said programming pulses increasing incrementally in voltage to increase the amount of charge on the floating gate until the amount of charge on the floating gate is equal to a desired amount of charge corresponding to a desired memory state of the memory cell;
• applying a plurality of verify pulses to the set of memory cells, each one of said verify pulses being applied after each one of the said programming pulses in an alternating manner, wherein said set of memory cells consists of a first subset of memory cells having a first desired memory state and a second subset of memory cells each having a respective second desired memory state that is less than the highest memory state;
• determining that the second subset of memory cells have been programmed to the respective second desired voltage memory state;
• and
• applying a maximum voltage programming pulse to each memory cell in the first subset of memory cells, wherein said maximum voltage programming pulse is equal to a voltage threshold level that results in the memory cell being in the first desired maximum voltage memory state.