MRAM architecture with a grounded write bit line and electrically isolated read bit line

A memory comprising:

• an array of random access memory cells arranged in a plurality of rows and columns, each of the random access memory cells comprising:
• a MTJ having a first terminal and a second terminal;
• and
• a transistor having a first current electrode coupled to the first terminal of the MTJ, a second current electrode, and a control electrode;
• wherein each column has:
• a write bit line associated therewith, wherein each write bit line passes in close proximity to each MTJ in the column to which the write bit line is associated, passes substantially in a first direction, and is coupled to the second terminal of each MTJ in each column;
• and
• a read bit line associated therewith for carrying stored data in a selected memory cell in the column by being coupled to the second current electrode of transistors in each column;
• and
• wherein each row has:
• a write word line associated therewith, wherein each row is in close proximity to each MTJ in the row with which it is associated and substantially in a second direction orthogonal to the first direction;
• and
• a read word line associated with each row coupled to the control electrode of the transistor to which it is associated in the row with which it is associated.

A method of reading a state of a selected memory cell, comprising:

• providing an array of random access memory cells arranged in a plurality of rows and columns, each of the random access memory cells comprising:
• a MTJ having a first terminal and a second terminal;
• and
• a transistor having a first current electrode coupled to the first terminal of the MTJ, a control electrode coupled to one of a plurality of word lines, and a second current electrode;
• providing a plurality of write lines aligned with the rows and columns in close proximity to the MTJs, wherein each MTJ is coupled to one of the plurality of write lines;
• providing a sense amplifier;
• and
• coupling the second current electrode of the transistor of the selected cell to the sense amplifier.

A memory, comprising:

• an array of random access memory cells arranged in a plurality of rows and columns, each of the random access memory cells comprising:
• a MTJ having a first terminal and a second terminal;
• and
• a transistor having a first current electrode coupled to the first terminal of the MTJ, a control electrode coupled to one of a plurality of word lines, and a second current electrode;
• a plurality of write lines aligned with the rows and columns in close proximity to the MTJs, wherein each MTJ is coupled to one of the plurality of write lines;
• and
• sensing means, coupled to each second current electrode of the transistors, for sensing states of selected memory cells.