Bridge-type magnetic random access memory (MRAM) latch

A magnetoresistive random access memory (MRAM) latching circuit comprising:

• a first terminal adapted to couple to a first portion of a first bit line;
• a second terminal adapted to couple to a second portion of the first bit line;
• a third terminal adapted to couple to a first portion of a second bit line;
• a fourth terminal adapted to couple to a second portion of the second bit line;
• a first output;
• a second output;
• and
• an input terminal adapted to receive a reset signal, where a first state of the reset signal couples the first output to the second output, and where a second state of the reset signal decouples the first output from the second output so that the first output and the second output latch in opposite directions in response to an imbalance in resistance between the first bit line and the second bit line.

A method of determining a magnetic state in a magnetoresistive random access memory (MRAM) cell comprising:

• applying a reset signal to an interface circuit such that at least one output of the interface circuit is reset to a balanced state;
• removing the reset signal;
• comparing an amount of resistance in a first portion of a first bit line to an amount of resistance in a first portion of a second bit line;
• comparing an amount of resistance in a second portion of the first bit line to an amount of resistance in a second portion of the second bit line;
• and
• generating an output with a logic state corresponding to the magnetic state stored in the cell based on the comparisons of the amount of resistance.

A method of latching a magnetic state in a magnetoresistive random access memory (MRAM) cell comprising:

• applying current to a word line corresponding to the MRAM cell;
• in a reset state, neutralizing cross-coupled feedback of an interface circuit to allow the interface circuit to balance in response to current applied through first and second portions of a first bit line and through first and second portions of a second bit line, where the current applied to the first bit line and the current applied through the second bit line are substantially equal, where the first bit line corresponds to the MRAM cell;
• and
• in a latched state, enabling cross-coupled feedback across the interface circuit that allows an imbalance in resistance from a stored state of the cell to latch the cell in a corresponding logical state.