Memory architecture with write circuitry and method therefor

A memory comprising:

• a plurality of memory cells organized in rows and columns, each of the plurality of memory cells located at intersections of the rows and columns;
• a plurality of write bit lines, each of the plurality of write bit lines having a first end and a second end, wherein a first write current flowing from the first end to the second end of a selected one of the plurality of write bit lines is used for placing a data value in a predetermined memory cell of the plurality of memory cells, the first end of each of the plurality of write bit lines being directly connected to a terminal for receiving a predetermined supply voltage;
• and
• a plurality of write word lines, each of the plurality of write word lines having a first end and a second end, wherein a second write current flowing from the first end to the second end of a selected one of the plurality of write word lines is used with the first write current for placing the data value in the predetermined memory cell of the plurality of memory cells, the first end of each of the plurality of write word lines being directly connected to the terminal for receiving the predetermined supply voltage, wherein the second end of the selected one of the plurality of write bit lines is coupled to a write circuit for placing the data value in the predetermined memory cell during a write cycle of the memory.

A memory comprising:

• a plurality of memory cells organized in rows and columns, each of the plurality of memory cells located at intersections of the rows and columns;
• and
• a plurality of write lines, each of the plurality of write lines coupled to a write circuit for placing a data value in a predetermined memory cell of the plurality of memory cells;
• the write circuit comprising:
• a first stage having an input terminal for receiving a reference voltage, and an output terminal for defining a reference current;
• and
• a second current mirror stage having an input terminal coupled to the output terminal of the first stage, an output terminal for providing a write current for placing the data value in the predetermined memory cell, and a control terminal for receiving a first timing signal.

In a memory having a plurality of magnetoresistive random access memory cells organized in rows and columns, a write line coupled to provide a write current used for writing a data value in a predetermined memory cell, a first switch for coupling the write line to a switchable current mirror in response to a decode signal, a method for writing the data value in the predetermined memory cell comprising the steps of:

• initiating a read operation of the predetermined memory cell;
• initiating a portion of a write toggling operation of the predetermined memory cell;
• comparing a presently stored data value at the predetermined memory cell to a new data value to be written to the predetermined memory cell and determining that the new data value is different than the presently stored data value;
• asserting the decode signal to make the first switch conductive;
• and
• enabling the switchable current mirror to provide a write current to the predetermined memory cell after the decode signal is asserted.