Ferroelectric transistor for storing two data bits

A non-volatile memory storage method comprising:

• providing an array of field effect transistors (FETs), wherein each FET in the array has a gate, drain, source, and substrate terminals, a first ferroelectric region between the gate and the source, and a second ferroelectric region between the gate and the drain, wherein the array is arranged in rows and columns, the gates of the FETs in a same row being coupled to a word line, the sources of FETs in a same column being coupled to a source bit line, and the drains of FETs in a same column being coupled to a drain bit line;
• applying a positive voltage to a selected word line, a negative voltage on a selected source bit line, ground potential on unselected word lines, unselected source lines and all drain bit lines such that a voltage greater than a coercive voltage is applied between the selected word line and selected source line, but a voltage less than the coercive voltage is applied between unselected word lines and selected source bit lines, between unselected word lines and unselected source bit lines, between unselected word lines and drain bit lines, selected word lines and drain bit lines, and selected word lines and unselected source bit lines to polarize said first ferroelectric region of a selected FET to a first state while leaving the polarization of all other ferroelectric materials in the array unchanged;
• applying a negative voltage to the selected word line, a positive voltage on the selected source bit line, ground potential on unselected word lines, unselected source lines and all drain bit lines such that a voltage greater than the coercive voltage is applied between the selected word line and selected source line, but a voltage less than the coercive voltage is applied between unselected word lines and selected source bit lines, between unselected word lines and unselected source bit lines, between unselected word lines and drain bit lines, selected word lines and drain bit lines, and selected word lines and unselected source bit lines to polarize said first ferroelectric region of the selected FET to a second state while leaving the polarization of all other ferroelectric materials in the array unchanged;
• applying a positive voltage to the selected word line, a negative voltage on the selected drain bit line, ground potential on unselected word lines, unselected drain lines and all source bit lines such that a voltage greater than the coercive voltage is applied between the selected word line and selected drain line, but a voltage less than the coercive voltage is applied between unselected word lines and selected drain bit lines, between unselected word lines and unselected drain bit lines, between unselected word lines and source bit lines, selected word lines and source bit lines, and selected word lines and unselected drain bit lines to polarize said second ferroelectric material of the selected FET to the first state while leaving the polarization of all other ferroelectric materials in the array unchanged;
• applying a negative voltage to the selected word line, a positive voltage on the selected drain bit line, ground potential on unselected word lines, unselected drain lines and all source bit lines such that a voltage greater than the coercive voltage is applied between the selected word line and selected drain line, but a voltage less than the coercive voltage is applied between unselected word lines and selected drain bit lines, between unselected word lines and unselected drain bit lines, between unselected word lines and source bit lines, selected word lines and source bit lines, and selected word lines and unselected drain bit lines to polarize said second ferroelectric material of the selected FET to second state while leaving the polarization of all other ferroelectric materials in the array unchanged;
• applying a positive voltage than less the coercive voltage on the selected word line, ground potential on the selected source bit line, a positive voltage no greater than the word line voltage on the selected drain bit line, and ground potential on unselected word lines, unselected source bit lines, and unselected drain bit lines to detect the polarization state of said first ferroelectric region, a high current between the selected source bit line and the selected drain bit line indicating first state and a low current between selected source bit line and selected drain bit line indicating the second state;
• and
• applying a positive voltage than less the coercive voltage on the selected word line, ground potential on the selected drain bit line, a positive voltage no greater than the word line voltage on the selected source bit line, and ground potential on unselected word lines, unselected source bit lines, and unselected drain bit lines to detect the polarization state of said second ferroelectric region, a high current between selected drain bit line and selected source bit line indicating first state and a low current between selected drain bit line and selected source bit line indicating second state.

A ferroelectric field effect transistor comprising:

• a source, a gate, a drain, and a channel;
• a gate dielectric layer including a first ferroelectric region overlaying the channel in the vicinity of the source, a second ferroelectric region overlaying the channel in the vicinity of the drain, and a non-ferroelectric dielectric overlaying the channel between the first and second ferroelectric region;
• and
• a conductive electrode layer overlaying said gate layer.

A method for the non-volatile storage of two data bits in a single FET transistor comprising:

• providing a field effect transistor (FET) having a gate, drain, source, and substrate, and having a first ferroelectric region between the gate and the source and a second ferroelectric region between the gate and the drain;
• selectively applying a voltage greater than a coercive voltage across the gate and the source to polarize said first ferroelectric region;
• selectively applying a voltage greater than the coercive voltage across the gate and the drain to polarize said second ferroelectric region;
• applying a positive voltage less than the coercive voltage on the gate, ground potential on the source, and a positive voltage no greater than the gate voltage on the drain to detect the polarization state of said first ferroelectric region;
• and
• applying a positive voltage less than the coercive voltage on the gate, ground potential on the drain, and a positive voltage no greater than the gate voltage on the source to detect the polarization state of said second ferroelectric region.

A non-volatile memory storage method comprising:

• providing an array of field effect transistors (FETs), wherein each FET in the array has a gate, drain, source, and substrate terminals, a first ferroelectric region between the gate and the source, and a second ferroelectric region between the gate and the drain, wherein the array is arranged in rows and columns, the gates of the FETs in a same row being coupled to a word line, the sources of FETs in a same column being coupled to a source bit line, and the drains of FETs in a same column being coupled to a drain bit line;
• applying a voltage greater than a coercive voltage across a selected word line and a selected source line to polarize said first ferroelectric region of a selected FET while leaving the polarization of all other ferroelectric materials in the array unchanged;
• applying a voltage greater than the coercive voltage across the selected word line and a selected drain line to polarize said second ferroelectric region of the selected FET while leaving the polarization of all other ferroelectric materials in the array unchanged;
• applying a positive voltage than less the coercive voltage on the selected word line, ground potential on the selected source bit line, a positive voltage no greater than the word line voltage on the selected drain bit line to detect the polarization state of said first ferroelectric region;
• and
• applying a positive voltage than less the coercive voltage on the selected word line, ground potential on the selected drain bit line, a positive voltage no greater than the word line voltage on the selected source bit line to detect the polarization state of said second ferroelectric region.