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US 6,714,434 B2Granted
Mid-array isolate circuit layout and method
AssigneeMicron Technology, Inc.
InventorDonald M. Morgan
Life of this patent
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Abstract
A double pitched array includes isolation devices to divide the array into subarrays, using the same space which is used for bit line twists. This addition allows the one-fourth of the bit line pair which will not be used to propagate signals to not be charged during a memory operation.
Claims14
A method of forming a memory, comprising:
- forming a first and a second subarray of memory cells on a semiconductor substrate;
- connecting a first plurality of even bit line pairs to a first set of sense amplifiers and to the subarrays of memory cells;
- connecting a second plurality of odd bit line pairs to a second set of sense amplifiers and to the subarrays of memory cells;
- connecting a first set of word lines to the first subarray;
- connecting a second set of word lines to the second subarray;
- and
- forming a plurality of isolation transistors between the first and the second subarrays to selectively disconnect a portion of each bit line pair from its respective sense amplifier.
4 more elements
A method for reducing power consumption in a memory array, comprising:
- isolating a first partial section of a first half of a plurality of bit lines connected to a first half of a plurality of sense amplifiers during a memory operation;
- and
- equilibrating the isolated sections of bit lines to a common potential.
A method of operating a double pitch sense amplifier integrated circuit, comprising:
- isolating a portion of a first plurality of bit lines from a first set of sense amplifiers;
- and
- equilibrating a potential to each of the portions of the isolated bit lines.
A method of operating an integrated circuit, comprising:
- initiating a memory operation on a memory array having a first subarray of memory cells and a second subarray of memory cells, each of the subarrays connected to a respective plurality of sense amplifiers;
- and
- isolating the plurality of sense amplifiers connected to one of the subarrays from the other of the subarrays.
A method of operating an integrated circuit, comprising:
- isolating a plurality of sense amplifiers connected to one of a plurality of arrays from other adjacent arrays to which the sense amplifiers are also connected;
- and
- isolating within the one of the plurality of arrays a first portion of a first plurality of bit line pairs.
A method, comprising:
- isolating a plurality of dual pitch sense amplifiers connected to bit lines of a near subarray and a far subarray from the far subarray;
- and
- initiating a memory operation using a word line of the near subarray during isolation of the far subarray.
Dependencies are inferred from the claim text.