Back to results
US 6,714,197 B1Granted
Processor having an arithmetic extension of an instruction set architecture
AssigneeMIPS Technologies, Inc.
InventorsRadhika Thekkath, G. Michael Uhler, Ying-wai Ho, Chandlee B. Harrell
Life of this patent
Estimating the term…
Abstract
A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.
Claims61
In a processor, a method for performing computer graphics calculations, said method comprising:
- representing a vertex in a computer graphics image with a plurality of world coordinates;
- transforming said plurality of world coordinates into a plurality of transformed world coordinates using a floating point reduction add instruction;
- and
- performing perspective division on said plurality of transformed world coordinates using a floating point reciprocal instruction, wherein said floating point reciprocal instruction processes a plurality of operands to generate a plurality of reduced precision reciprocal values.
1 more element
In a processor, a method for performing computer graphics calculations, said method comprising:
- representing a vertex in a computer graphics image with a plurality of surface normal coordinates;
- transforming said plurality of surface normal coordinates into a plurality of transformed surface normal coordinates using a floating point reduction add instruction;
- and
- normalizing said plurality of transformed surface normal coordinates using a floating point reciprocal square root instruction, wherein said reciprocal square root instruction processes a plurality of operands to generate a plurality of reduced precision reciprocal square root values.
1 more element
A processor for computer graphics calculations, said processor comprising:
- a bus;
- an instruction dispatch unit coupled to said bus, said instruction dispatch unit for dispatching instructions to a floating point unit;
- and
- said floating point unit coupled to said bus, said floating point unit for executing said instructions to implement a method for performing computer graphics calculations, said method comprising:
- representing a vertex in a computer graphics image with a plurality of world coordinates;
- transforming said plurality of world coordinates into a plurality of transformed world coordinates using a floating point reduction add instruction;
- and
- performing perspective division on said plurality of transformed world coordinates using a floating point reciprocal instruction, wherein said floating point reciprocal instruction processes a plurality of operands to generate a plurality of reduced precision reciprocal values.
5 more elements
A processor for computer graphics calculations, said processor comprising:
- a bus;
- an instruction dispatch unit coupled to said bus, said instruction dispatch unit for dispatching instructions to a floating point unit;
- and
- said floating point unit coupled to said bus, said floating point unit for executing said instructions to implement a method for performing computer graphics calculations, said method comprising:
- representing a vertex in a computer graphics image with a plurality of surface normal coordinates;
- transforming said plurality of surface normal coordinates into a plurality of transformed surface normal coordinates using a floating point reduction add instruction;
- normalizing said plurality of transformed surface normal coordinates using a floating point reciprocal square root instruction, wherein said reciprocal square root instruction processes a plurality of operands to generate a plurality of reduced precision reciprocal square root values;
- computing a dot product between said plurality of transformed surface normal coordinates and a vector using said floating point reduction add instruction;
- computing a halfway vector in a lighting calculation;
- and
- normalizing said halfway vector using said floating point reciprocal square root instruction.
8 more elements
In a processor including a memory and an execution unit (“EU”), a method for determining a plurality of reduced precision values from a plurality of operands comprising:
- storing a first instruction in said memory, said first instruction being formatted to operate on said plurality of operands in parallel;
- dispatching said first instruction for execution by said EU;
- and
- executing said first instruction in said EU, wherein said executing includes:
- accessing in parallel a plurality of lookup tables in said EU to obtain a plurality of first intermediate results, wherein each lookup table is accessed with a first portion of a corresponding operand;
- modifying in parallel a second portion of each of said plurality of operands to obtain a plurality of second intermediate results;
- and
- arithmetically combining in parallel said plurality of first intermediate results with said plurality of second intermediate results to obtain said plurality of reduced precision values.
5 more elements
A system comprising:
- a processor;
- a memory, coupled to said processor, for storing a first plurality of instructions that enables said processor to perform select operations, wherein said first plurality of instructions includes:
- a first instruction that enables said processor to combine a first plurality of operands in accordance with a first method, said first method comprising:
- reading a first operand from a first position of a first data set and a second operand from a second position of said first data set;
- combining said first operand and said second operand of said first data set, and placing the result in a first position of a first destination data set;
- reading a third operand from a first position of a second data set and a fourth operand from a second position of said second data set;
- and
- combining said third operand and said fourth operand of said second data set, and placing the result in a second position of said first destination data set;
- and
- a second instruction that enables said processor to determine a plurality of reduced precision values from a second plurality of operands.
7 more elements
A system comprising:
- a memory for holding a plurality of instructions, said plurality of instructions including a first, second and third instruction;
- and
- a processor, coupled to said memory, for executing said plurality of instructions, wherein said processor includes:
- a first means for executing said first instruction to produce a plurality of reduced precision reciprocal values;
- a second means for executing said second instruction to produce a plurality of reduced precision reciprocal square root values;
- and
- a third means for executing said third instruction for performing a floating point reduction computation, wherein said computation is a function selected from the group consisting essentially of add and multiply.
4 more elements
A computer program product comprising a computer readable medium having a plurality of instructions stored thereon, the plurality of instructions for enabling a processor to perform certain operations, wherein the plurality of instructions include:
- a first instruction that enables said processor to combine a first plurality of operands in accordance with a method, said method comprising:
- reading a first operand from a first position of a first data set and a second operand from a second position of said first data set;
- combining said first operand and said second operand, and placing the result in a first position of a destination data set;
- reading a third operand from a first position of a second data set and a fourth operand from a second position of said second data set;
- and
- combining said third operand and said fourth operand, and
- placing the result in a second position of said destination data set;
- and
- a second instruction that enables said processor to determine a plurality of reduced precision values from a second plurality of operands.
6 more elements
Dependencies are inferred from the claim text.