Liquid crystal display apparatus having level conversion circuit

A liquid crystal display apparatus comprising:

• a display unit comprised of pixel elements arranged in a matrix;
• a signal circuit and a scanning circuit for driving the pixel elements;
• a first level conversion circuit connected to the signal circuit and the scanning circuit, to perform level conversion of data signals and transmit to the signal circuit and the scanning circuit to drive the pixel elements;
• a second level conversion circuit connected to at least one of the signal circuit and the scanning circuit, to perform level conversion of differential clock signals to control the transmission of data signals to the signal circuit to drive the pixel elements;
• and
• a latch circuit connected to the first level conversion circuit and the second level conversion circuit, to latch the data signals transmitted from the first level conversion circuit to the signal circuit in accordance with clock signals outputted from the second level conversion circuit;
• wherein:
• the second conversion circuit converts the differential clock signals having a low voltage amplitude into clock signals having a high voltage amplitude, and outputs the clock signals having the high voltage amplitude to the latch circuit, and
• the first conversion circuit converts input data signals having a low voltage amplitude to data signals having a high voltage amplitude, and outputs the data signals having the high voltage amplitude to the latch circuit.

A display apparatus comprising:

• a display unit comprised of pixel elements arranged in a matrix;
• a signal circuit and a scanning circuit for driving the pixel elements;
• a multi-input type level conversion circuit connected to the signal circuit and the scanning circuit, to perform level conversion of data signals and transmit to the signal circuit and the scanning circuit to drive the pixel elements;
• and
• a differential input type level conversion circuit connected to at least one of the signal circuit and the scanning circuit, to perform level conversion of differential clock signals to control the transmission of data signals to the signal circuit to drive the pixel elements, wherein the differential input type level conversion circuit includes a level conversion unit comprising:
• a first transistor and a second transistor connected in parallel, having respective gate electrodes coupled to receive a bias voltage;
• and
• a first resistance element and a second resistance element connected in parallel, and disposed between respective drain electrodes of the first transistor and the second transistor and a power supply terminal;
• wherein respective source electrodes of the first transistor and the second transistor are coupled to receive clock signals having a mutually different polarity and a low voltage amplitude, and the respective drain electrodes of the first transistor and the second transistor are coupled to output clock signals having a mutually different polarity and a high voltage amplitude.

A display apparatus comprising:

• a display unit comprised of pixel elements arranged in a matrix;
• a signal circuit and a scanning circuit for driving the pixel elements;
• a multi-input type level conversion circuit connected to the signal circuit and the scanning circuit, to perform level conversion of data signals and transmit to the signal circuit and the scanning circuit to drive the pixel elements;
• and
• a differential input type level conversion circuit connected to at least one of the signal circuit and the scanning circuit, to perform level conversion of differential clock signals to control the transmission of data signals to the signal circuit to drive the pixel elements, wherein the differential input type level conversion circuit comprises:
• a plurality of transistors each having a gate electrode coupled to receive to a bias voltage;
• and
• a plurality of resistance elements each connected between a drain electrode of a respective transistor and a power supply terminal;
• wherein each of a plurality of input pixel element drive signals is inputted to the source electrode of a respective one of the transistors;
• wherein each of control signals is outputted from the drain electrode of a respective transistor;
• and
• wherein amplitudes of output control signals are higher than amplitudes of input control signals.

A liquid crystal display apparatus comprising:

• a display unit comprised of pixel elements arranged in a matrix;
• a signal circuit and a scanning circuit for driving the pixel elements;
• a first level conversion circuit connected to the signal circuit and the scanning circuit, to perform level conversion of data signals and transmit to the signal circuit and the scanning circuit to drive the pixel elements;
• a second level conversion circuit connected to at least one of the signal circuit and the scanning circuit, to perform level conversion of differential clock signals to control the transmission of data signals to the signal circuit to drive the pixel elements;
• wherein the first level conversion circuit is a multi-input type level conversion circuit and the second conversion circuit is a differential input type level conversion circuit which includes a level conversion unit comprising:
• a first transistor and a second transistor connected in parallel, having respective gate electrodes coupled to receive a bias voltage;
• and
• a first resistance element and a second resistance element connected in parallel, and disposed between respective drain electrodes of the first transistor and the second transistor and a power supply terminal;
• wherein respective source electrodes of the first transistor and the second transistor are coupled to receive clock signals having a mutually different polarity and a low voltage amplitude, and the respective drain electrodes of the first transistor and the second transistor are coupled to output clock signals having a mutually different polarity and a high voltage amplitude.

A liquid crystal display (LCD) panel comprising:

• a display unit comprised of pixel elements arranged in a matrix;
• a scanning circuit and a signal circuit arranged to drive pixel elements;
• a multi-input type level conversion circuit arranged to generate control signals and to convert image signals having a low voltage amplitude into image signals having a high voltage amplitude;
• a differential input type level conversion circuit arranged to convert differential clock signals having a low voltage amplitude into clock signals having a high voltage amplitude;
• and
• a latch circuit arranged to latch the image signals having the high voltage amplitude to the signal circuit in accordance with the clock signals having the high voltage amplitude;
• wherein the signal circuit and the scanning circuit are driven to provide a visual display of images corresponding to the image signals latched from the latch circuit in accordance with the control signals generated from the multi-input type level conversion circuit.