US 6,714,152 B1 · Pipelined analog-to-digital converter

Abstract

The present invention is a pipelined analog-to-digital converter (Pipelined ADC) for converting a first analog signal to a digital data. The converter comprises at least one first stage circuit, at least one second stage circuit, a third stage circuit, and a code adder. Each of the first stage circuits has a first converting rate for converting a first analog signal to at least one digital code and generating a second analog signal. The second stage circuits are serially connected after the first stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate for converting the second analog signal to at least two digital codes and generating a third analog signal. The third stage circuit serially connected after the second stage circuits is used for converting the third analog signal to at least one digital code. The code adder is used for combining the digital codes to generate the digital data. Thus, the later half stage circuits of the Pipelined ADC has a higher converting rate, so the converter of the present invention can reduce the number of the stage circuits needed and further reduces the area of the converter.

Claims14

Dependent claims

A Pipelined Analog-to-Digital Converter (Pipelined ADC) for converting a first analog signal to a digital data, said converter comprising:

A group of first stage circuits for converting said first analog signal to at least one digital output code and generating a second analog signal, said group of first stage circuits comprising at least one first stage circuit, each of said first stage circuits having a first converting rate, so as to output one digital output code in one clock;
A group of second stage circuits series connecting after said group of first stage circuits, used for converting said second analog signal to at least two digital output codes, and generating a third analog signal, said group of second stage circuits comprising at least one second stage circuit, each of said second stage circuits having a second converting rate which is higher than said first converting rate, so as to output average at least two digital output codes in one clock;
A third stage circuit series connecting after said group of second stage circuits, used for converting said third analog signal to at least one digital output code;
and
A digital output code integrating device, used for integrating said digital output codes converted by said group of first stage circuits, said group of second stage circuits, and said third stage circuit.

2 more elements

Dependencies are inferred from the claim text.

Pipelined analog-to-digital converter

Life of this patent

Pipelined analog-to-digital converter

Life of this patent

Abstract

Claims14