Buffer circuit for op amp output stage

An operational amplifier (op amp), comprising:

• an input stage which converts a differential input voltage to a differential current which varies with said differential input voltage,
• a gain stage comprising a plurality of field-effect transistors (FETs) arranged in a folded-cascode configuration which receives said differential current from said input stage, and
• an output stage, comprising:
• a current switch comprising:
• at least one NMOS PET, said NMOS FETs receiving respective bias voltages at their gates and having their drain-source circuits connected in series between a first node and a second node,
• at least one PMOS FET, said PMOS FETs receiving respective bias voltages at their gates and having their drain-source circuits connected in series between said first node and said second node, said differential current applied across said first and second nodes via said gain stage,
• said bias voltages selected such that said cascoded NMOS FETs and said cascoded PMOS FETs conduct approximately equal currents when said differential current is zero, said current switch producing first and second voltages at said first and second nodes, respectively, which vary with said differential current,
• first and second buffer amplifiers which receive said first and second voltages and produce respective outputs which vary with said first and second voltages,
• first and second complementary output FETs connected in a back-to-back common-source configuration between first and second supply voltages, said first and second complementary output FETs arranged to conduct respective currents to their common output node in response to the outputs of said first and second buffer amplifiers, respectively, said common output node being the output of said operational amplifier, and
• a frequency compensation scheme connected between said current-switch and said common output node.

A fully differential operational amplifier (op amp), comprising:

• an input stage which converts a differential input voltage to a differential current which varies with said differential input voltage, said differential current having first and second signal lines,
• first and second gain stages, each of which comprises a plurality of field-effect transistors (FETs) arranged in a folded-cascode configuration and is connected to a respective one of said first and second differential current signal lines, and
• first and second output stages, each of which comprises:
• a current switch which receives the current on a respective one of said first and second differential current signal lines via a respective one of said gain stages and produces first and second voltages which vary with said received current at first and second nodes, respectively,
• first and second buffer amplifiers which receive said first and second voltages and produce respective outputs which vary with said first and second voltages, and
• first and second complementary output transistors connected together at a common output node and arranged to conduct respective currents to said common output node in response to the outputs of said first and second buffer amplifiers, respectively,
• the common output nodes of said first and second output stages being the outputs of said op amp.