Master slave flip-flop circuit functioning as edge trigger flip-flop
AssigneesRenesas Technology Corp., Mitsubishi Electric System LSI Design Corporation
InventorMasahiro Araki
Life of this patent
Estimating the term…
Abstract
In a master latch circuit, input data signal is received in a data through state and is held in a data holding state as output data signal. In a slave latch circuit, the output data signal is received in a data through state and is held and output in a data holding state. In a circuit setting control unit, in response to a clock signal, the disconnection of a first line from a power source and the connection of a second line to a ground terminal in an NMOS transistor are performed to set the master latch circuit and the slave latch circuit to the data through state and the data holding state respectively, and the connection of the first line and the disconnection of the second line are performed to change the states of the latch circuits.
Claims8
A master slave flip-flop circuit comprising:
- a master latch circuit for receiving input data in a data through state and holding the input data as master output data in a data holding state;
- a slave latch circuit for receiving the master output data held by the master latch circuit in a data through state, holding the master output data as slave output data in a data holding state, and outputting the slave output data;
- and
- circuit state setting control means for performing both the disconnection of a first line connected to both the master latch circuit and the slave latch circuit from a line set to a first electric potential and the connection of a second line connected to both the master latch circuit and the slave latch circuit to a line set to a second electric potential in response to a first level of a clock signal to set the master latch circuit to the data through state and to set the slave latch circuit to the data holding state and performing both the connection of the first line to the line set to the first electric potential and the disconnection of the second line from the line set to the second electric potential in response to a second level of the clock signal to set the master latch circuit to the data holding state and to set the slave latch circuit to the data through state.
Dependencies are inferred from the claim text.