Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices

A clock generator circuit, comprising:

• a plurality of series-connected delay elements each having an input terminal and an output terminal, the input terminal of the first of the delay elements being coupled to receive an input clock signal;
• a plurality of driver circuits each having an input terminal coupled to the output terminal of a respective delay element, the driver circuits outputting at respective output terminals respective clock signals having phases relative to the input clock signal that are different from each other;
• and
• a plurality of signal paths coupling the output terminals of respective driver circuits to respective circuit nodes, the propagation delays of at least some of the signals paths being different from the propagation delays of others of the signal paths.

An electronic assembly comprising:

• a locked-loop receiving a clock signal and generating a processed clock signal responsive thereto;
• a delay circuit receiving the processed clock signal from the locked-loop, the delay circuit having a plurality of output terminals generating respective delayed clock signals that have respective phases with respect to the processed clock signal that differ from each other;
• a plurality of driver circuits each having an input terminal coupled to a respective output terminal of the delay circuit, the driver circuits outputting at respective output terminals respective clock signals having phases relative to the processed clock signal that are different from each other;
• a plurality of clocked circuits structured to operate responsive to a received clock signal;
• and
• a respective signal path coupled between a plurality of the clocked circuits and respective output terminals of the driver circuits, the signal propagation delays of at least some of the signal paths being different from the propagation delays of others of the signal paths.

An electronic assembly comprising:

• a delay circuit receiving an input clock signal, the delay circuit having a plurality of output terminals generating respective delayed clock signals that have respective phases relative to the input clock signal that differ from each other;
• a plurality of driver circuits each having an input terminal coupled to a respective output terminal of the delay circuit, the driver circuits outputting at respective output terminals respective clock signals having phases relative to the input clock signal that are different from each other;
• a plurality of clocked circuits structured to operate responsive to a received clock signal;
• and
• a respective signal path coupled between the output terminal of each of the driver circuits and a respective one of the clocked circuits, the propagation delays of at least some of the signal paths being different from the propagation delays of others of the signal paths.

A memory module, comprising:

• a substrate;
• a locked-loop mounted on the substrate, the locked-loop receiving a clock signal and generating a processed clock signal responsive thereto;
• a delay circuit mounted on the substrate receiving the processed clock signal from the locked-loop, the delay circuit having a plurality of output terminals generating respective delayed clock signals that have respective phases with respect to the processed clock signal that differ from each other;
• a plurality of driver circuits mounted on the substrate, each driver circuit having an input terminal coupled to a respective output terminal of the delay circuit, the driver circuits outputting at respective output terminals respective clock signals having phases relative to the processed clock signal that are different from each other;
• a plurality of memory devices mounted on the substrate, each of the memory devices structured to operate responsive to a received clock signal;
• and
• a signal path structured to couple a respective delayed clock signal from the output terminal of a respective one of the driver circuits to a respective one of the memory devices, the signal paths coupled to at least some of the memory devices having propagation delays that are different from the propagation delays of others of the signal paths coupled to others of the memory devices.

A computer system, comprising:

• computer circuitry operable to perform computing functions;
• at least one input device coupled to the computer circuitry;
• at least one output device coupled to the computer circuitry;
• at least one data storage devices coupled to the computer circuitry;
• and
• a memory module, comprising:
• a substrate;
• a locked-loop mounted on the substrate, the locked-loop receiving a clock signal and generating a processed clock signal responsive thereto;
• a delay circuit mounted on the substrate receiving the processed clock signal from the locked-loop, the delay circuit having a plurality of output terminals generating respective delayed clock signals that have respective phases with respect to the processed clock signal that differ from each other;
• a plurality of driver circuits mounted on the substrate, each driver circuit having an input terminal coupled to a respective output terminal of the delay circuit, the driver circuits outputting at respective output terminals respective clock signals having phases relative to the processed clock signal that are different from each other;
• a plurality of memory devices mounted on the substrate, each of the memory devices structured to operate responsive to a received clock signal;
• and
• a signal path structured to couple a respective delayed clock signal from the output terminal of a respective one of the driver circuits to a respective one of the memory devices, the signal paths coupled to at least some of the memory devices having propagation delays that are different from the propagation delays of others of the signal paths coupled to others of the memory devices.

A method of applying a clock signal to a plurality of clocked circuits, comprising:

• generating a plurality of clock signals having phases that are different from each other;
• switching a plurality of driver circuits responsive to each transition of a respective one of the clock signals;
• and
• coupling each of the driver circuits through a respective signal path to a respective clocked circuit, the propagation delays of each of the signal paths being inversely proportional to the phase of the clock signal coupled through the signal path.