US 6,714,057 B2Granted

Multi-purpose digital frequency synthesizer circuit for a programmable logic device

AssigneeXilinx, Inc.

InventorAndy T. Nguyen

Life of this patent

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Abstract

A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

Claims18

Dependent claims

A digital frequency synthesizer (DFS) circuit, comprising:

a true clock input terminal;
a complement clock input terminal;
an output clock terminal;
a pulse generator circuit having an input terminal coupled to the true clock input terminal and further having an output terminal;
a control circuit having a first input terminal coupled to the output terminal of the pulse generator circuit, a second input terminal coupled to the true clock input terminal, a ground select input terminal, and first and second output terminals;
a first passgate coupled between the true clock input terminal and the output clock terminal, the first passgate having a control terminal coupled to the first output terminal of the control circuit;
a second passgate coupled between the complement clock input terminal and the output clock terminal, the second passgate having a control terminal coupled to the second output terminal of the control circuit;
a keeper circuit having an output terminal coupled to the output clock terminal;
and
a ground control circuit having a data terminal coupled to the output clock terminal and a control terminal coupled to the ground select input terminal of the control circuit.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/306,149Filed 26 Nov 2002 · continuation in part
Priority: 28 Aug 2001
Published: US 2003/0048118 A112 Jun 2003
Granted: 30 Mar 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
H03K 23/00
Pulse counters comprising counting chains
G06F
Computing and data processing
H03K
Pulse technique

Family

Application09/942,230Parent of this continuation-in-part · filed 28 Aug 2001
Application10/193,070Parent of this continuation-in-part · filed 10 Jul 2002
US 2003/0107415 A1Pre-grant publication · published 12 Jun 2003
US 6,445,228 B1Parent of this continuation-in-part
US 2003/0048118 A1Published application
US 6,744,289 B2Related patent
US 6,714,057 B2This patent

From the US filing history. Foreign family members aren’t listed.