Frequency division/multiplication with jitter minimization
AssigneeBroadcom Corporation
InventorsSiavash Fallahi, Myles Wakayama, Pieter Vorenkamp
Life of this patent
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Abstract
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.
Claims18
An integrated low jitter frequency multiplication/division electronic circuit for multiplying/dividing a frequency of a reference signal, the circuit comprising:
- phase-lock loop (PLL) means for producing M clock phases from the reference signal;
- counter means for producing a count signal from the M clock phases;
- signal shifter means for producing a shifted signal based on the M clock phases and the count signal;
- and
- divider means for producing a feedback signal for the PLL based on the shifted signal.
A circuit for multiplying/dividing frequency of a reference signal, comprising:
- means for shifting the reference signal by one phase every K/M cycle so that the reference signal is at least one of decreased by (K+1)/K and increased by K/(K+1) to produce a shifted signal;
- means for dividing the shifted signal by N to produce a feedback signal;
- means for extending the period of the reference signal at least to T+T/M for frequency division and to T+T/M for frequency multiplication;
- and
- means for outputting M number of clock phases from a reference signal using a phase-lock loop (PLL) having feedback.
A frequency divider electronic circuit for dividing frequency of a reference signal by a non-integer number, the circuit comprising:
- clock generator means for receiving the reference signal and for generating M clock phases based on the reference signal;
- signal shifter means for receiving the M clock phases and a count signal and for outputting a shifted signal;
- divider means for receiving the shifted signal and for producing a feedback signal for the clock generator;
- and
- counter means for receiving the M number of clock phases and outputting the count signal to the signal shifter.
Dependencies are inferred from the claim text.