Method and apparatus for passive component minimization of connector pins in a computer system

A method for passive component minimization of connector pins comprising:

• coupling at least one selection switch via passive components to a single connector pin of a daughterboard, the connector pin being of a first origin and the at least one selection switch for selectively connecting the passive components to the single connector pin representative of a prescribed state of a number of states of the daughterboard, the prescribed state of the number of prescribed states being selectable as a function of the at least one selection switch and the passive components;
• coupling a supply voltage and pull-up resistor circuit to a single connector pin of a motherboard, the connector pin being of a second origin;
• and
• coupling decoding circuitry to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data, wherein responsive to a mating of the daughterboard connector pin with the motherboard connector pin, the decoding circuitry converts voltage level data present at the motherboard connector pin into binary data representative of a current state of the daughterboard as a function of the at least one selection switch and passive components of the daughterboard.

An apparatus having a passive component minimization of connector pins configuration comprising:

• a secondary printed circuit board including at least one selection switch coupled via passive components to a single connector pin of a first origin, the at least one selection switch for selectively connecting the passive components to the single connector pin representative of a prescribed state of a number of states of said secondary printed circuit board, the prescribed state of the number of prescribed states being selectable as a function of the at least one selection switch and the passive components;
• and
• a primary printed circuit board including a supply voltage and pull-up resistor circuit coupled to a single connector pin of a second origin, said primary circuit board further including decoding circuitry coupled to the primary circuit board connector pin for decoding a voltage level of the primary circuit board connector pin into binary data, wherein responsive to a mating of the secondary printed circuit board connector pin with the primary printed circuit board connector pin, the decoding circuitry converts voltage level data present at the primary printed circuit board connector pin into binary data representative of a current state of said secondary printed circuit board as a function of the at least one selection switch and passive components of said secondary printed circuit board.