Back to results
US 6,714,048 B1Granted
Input buffer with voltage clamping for compatibility
AssigneeLattice Semiconductor Corporation
InventorBradley A. Sharpe-Geisler
Life of this patent
Estimating the term…
Abstract
An input/output buffer is provided with input buffer circuitry which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. The voltage and current on the output of the input buffer as controlled by the CMOS transistors is clamped to levels depending on a mode select signal applied to selectively provide different output levels compatible with PCI, GTL, PECL, ECL and SSTI signals.
Claims20
A buffer comprising:
- a first mode select input;
- a second mode select input;
- a buffer input (IN);
- a buffer output (OUT);
- a first voltage clamp connected to the first mode select input, the buffer input, and the buffer output (OUT), the first voltage clamp limiting a voltage of a signal at the buffer output depending on a first select signal received at the first mode select input when a signal is received at the buffer input in a first state;
- and
- a second voltage clamp connected to the second mode select input, the buffer input, and the buffer output, the second voltage clamp limiting a voltage of a signal at the buffer output depending on a second select signal received at the second mode select input when a signal is received at the buffer input in a second state.
4 more elements
A buffer comprising:
- a first mode select input to receive a first mode select signal;
- a second mode select input to receive a second mode select signal;
- an buffer input to receive a data signal input;
- a buffer output;
- means for connecting a first power supply terminal for receiving a first voltage potential VDD to the buffer output so that a voltage on the buffer output is selectable between a first high voltage having a value less than the first voltage potential VDD and a second high voltage having a value of the first voltage potential VDD when the data signal is received in a first state, the selection between the first high voltage and the second high voltage being dependent on the first mode select signal;
- and
- means for connecting a second power supply terminal for receiving a second voltage potential VSS to the buffer output so that a voltage on the buffer output is selectable between a first low voltage having a value less than the second voltage potential VSS and a second low voltage having a value of the second voltage potential VSS when the data signal is received in a second state, the selection between the first low voltage and the second low voltage being dependent on the second mode select signal.
4 more elements
A buffer comprising:
- an input node (IN) for receiving an input signal which may be one of a Peripheral Component Interconnect (PCI) signal, a Gunning Transceiver Logic (GTL) signal, and a Pseudo Emitter Coupled Logic (PECL) signal;
- a first mode select node (GTL);
- a second mode select node (PECL);
- a first CMOS buffer comprising:
- a first PMOS pull up transistor (13) having a source to drain path coupled between a first power supply terminal (VDD) and an output node (OUT), and having a gate;
- a first PMOS pull up control transistor (10) having a source to drain path coupling the first power supply terminal (VDD) to the source to drain path of the first PMOS pull up transistor;
- a first NMOS pull down transistor (16) having a source to drain path coupled between the output node (OUT) and a second power supply terminal (VSS), and having a gate;
- and
- an first NMOS pull down control transistor (18) having a source to drain path coupling the second power supply terminal (VSS) to the source to drain path of the first NMOS pull down transistor;
- a second CMOS buffer comprising:
- a second PMOS pull up transistor (8) having a source to drain path coupled between the first power supply terminal (VDD) and the output node (OUT), and having a gate;
- and
- a second NMOS pull down transistor (22) having a source to drain path coupled between the output node (OUT) and the second power supply terminal (VSS), and having a gate;
- a first switching circuit configured for coupling the input node (IN) to control the gate of the first pull up transistor and applying a first reference (VPRF) to the gate of the first PMOS pull up control transistor so that a voltage less than a voltage on the first power supply terminal (VDD) is applied to the source to drain path of the first pull up transistor when a select signal is applied to the first and second mode select nodes indicating a GTL mode;
- a second switching circuit configured for coupling the input node (IN) to control the gate of the first pull down transistor and applying a second reference (VNRF) to the gate of the first NMOS pull down control transistor (18) so that a voltage greater than a voltage on the second power supply terminal (VSS) is applied to the source to drain path of the first pull down transistor when a select signal is applied to the first and second mode select nodes indicating a PECL mode;
- a third switching circuit configured for coupling the input node (IN) to the gate of the second pull up transistor when a select signal is applied to the first and second select nodes indicating one of a PCI mode and the PECL mode;
- and
- a fourth switching circuit configured for coupling the input node (IN) node to the gate of the second pull down transistor when a select signal is applied to the first and second select nodes indicating one of the PCI mode and the GTL mode.
15 more elements
Dependencies are inferred from the claim text.