Level shifter and electro-optical apparatus incorporating the same

A level shifter, comprising:

• a second capacitor having a first end and a second end, a low-amplitude logic signal being input to the first end of the second capacitor;
• a second offset circuit to apply a second offset voltage to the second end of the second capacitor;
• and
• first and second switching elements connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal, the first switching element turning on when the low-amplitude logic signal is L level, and the second switching element turning on when a signal voltage at the second end of the second capacitor is at or above a second threshold voltage, which is set to be higher than the second offset voltage,
• the first switching element being a P-channel transistor and the second switching element being an N-channel transistor,
• and the second offset circuit being implemented by a P-channel transistor and an N-channel transistor connected in series between the supply line of the power supply voltage and the supply line of the reference voltage, a voltage at a node therebetween serving as the second offset voltage and as gate voltages of the P-channel transistor and the N-channel transistor.

A level shifter, comprising:

• a first capacitor having a first end and a second end, a low-amplitude logic signal being input to the first end of the first capacitor;
• a first offset circuit to apply a first offset voltage to the second end of the first capacitor;
• and
• first and second switching elements connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal, the first switching element turning on if a signal voltage at the second end of the first capacitor is at or below a first threshold voltage, which is set to be lower than the first offset voltage, and the second switching element turning on when the low-amplitude logic signal is at H level,
• the first switching element being a P-channel transistor and the second switching element being an N-channel transistor,
• and the first offset circuit being implemented by a P-channel transistor and an N-channel transistor connected in series between the supply line of the power supply voltage and the supply line of the reference voltage a voltage at a node therebetween serving as the first offset voltage and as gate voltages of the P-channel transistor and the N-channel transistor.

A level shifter, comprising:

• a first capacitor having a first end and a second end, a low-amplitude logic signal being input to the first end of the first capacitor;
• a first offset circuit to apply a first offset voltage to the second end of the first capacitor;
• a second capacitor having a first end and a second end, the low-amplitude logic signal being input to the first end of the second capacitor;
• a second offset circuit to apply a second offset voltage to the second end of the second capacitor;
• and
• first and second switching elements connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, the first switching element being connected to the second end of the first capacitor, the second switching element being connected to the second end of the second capacitor, the first offset circuit including an N-channel transistor connected to a common drain from the first and second switching elements.

A level shifter, comprising:

• a first capacitor having a first end and a second end, a low-amplitude logic signal being input to the first end of the first capacitor;
• a first offset circuit to apply a first offset voltage to the second end of the first capacitor;
• a second capacitor having a first end and a second end, the low-amplitude logic signal being input to the first end of the second capacitor;
• a second offset circuit to apply a second offset voltage to the second end of the second capacitor;
• and
• first and second switching elements connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, the first switching element being connected to the second end of the first capacitor, the second switching element being connected to the second end of the second capacitor, the second offset circuit including a P-channel transistor connected to a common drain from the first and second switching elements.