Static transmission of FAST14 logic 1-of-N signals

A system that includes an apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• a storage element having a static output signal;
• an NDL gate that further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology, said NDL gate receives said static output signal;
• and
• a transmission path coupled to said storage element and to said NDL gate that carries said static output signal, said transmission path is characterized by a multi-cycle path timing constraint that creates one or more tool-specific verification tests.

A method to make an apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• providing a storage element having a static output signal;
• providing an NDL gate that further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology, said NDL gate receives said static output signal;
• and
• coupling a transmission path to said storage element and to said NDL gate that carries said static output signal, said transmission path is characterized by a multi-cycle path timing constraint that creates one or more tool-specific verification tests.

A method to use an apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• generating a static output signal from a storage element;
• receiving said static output signal at an NDL gate that further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology;
• and
• carrying said static output signal using a transmission path coupled to said storage element and to said NDL gate, said transmission path is characterized by a multi-cycle path timing constraint that creates one or more tool-specific verification tests.

An apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• a storage element having a first static output signal that holds its value for at least two successive clock cycles;
• a dynamic mux that selects one of the following every clock cycle:
• either said first static output signal or a second static signal that holds its value for at least two successive clock cycles;
• an NDL gate coupled to said dynamic mux that receives said first static output signal and said second static output signal, said NDL gate further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology;
• and
• a transmission path coupled to said storage element, to said dynamic mux, and to said NDL gate, said transmission path carries said first static output signal, said transmission path is characterized by a multi-cycle path timing constraint that further comprises a pragma that is interpreted by a PATHMILL compiler to create statements that check the set-up and hold times of said first static signal relative to the rising edge or falling edge of user-specified clock signal pulses, said pragma is interpreted by a compiler to create statements that test the behavior of the apparatus during the clock signal pulses other than said user-specified clock signal pulses.

A system that includes an apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• a storage element having a first static output signal that holds its value for at least two successive clock cycles;
• a dynamic mux that selects one of the following every clock cycle:
• either said first static output signal or a second static signal that holds its value for at least two successive clock cycles;
• an NDL gate coupled to said dynamic mux that receives said first static output signal and said second static output signal, said NDL gate further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology;
• and
• a transmission path coupled to said storage element, to said dynamic mux, and to said NDL gate, said transmission path carries said first static output signal, said transmission path is characterized by a multi-cycle path timing constraint that further comprises a pragma that is interpreted by a PATHMILL compiler to create statements that check the set-up and hold times of said first static signal relative to the rising edge or falling edge of user-specified clock signal pulses, said pragma is interpreted by a compiler to create statements that test the behavior of the apparatus during the clock signal pulses other than said user-specified clock signal pulses.

A method to make an apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• providing a storage element having a first static output signal that holds its value for at least two successive clock cycles;
• providing a dynamic mux that selects one of the following every clock cycle:
• either said first static output signal or a second static signal that holds its value for at least two successive clock cycles;
• coupling an NDL gate to said dynamic mux that receives said first static output signal and said second static output signal, said NDL gate further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology;
• and
• coupling a transmission path to said storage element, to said dynamic mux, and to said NDL gate, said transmission path carries said first static output signal, said transmission path is characterized by a multi-cycle path timing constraint that further comprises a pragma that is interpreted by a PATHMILL compiler to create statements that check the set-up and hold times of said first static signal relative to the rising edge or falling edge of user-specified clock signal pulses, said pragma is interpreted by a compiler to create statements that test the behavior of the apparatus during the clock signal pulses other than said user-specified clock signal pulses.

A method to use an apparatus for the static transmission of FAST14 logic's 1-of-N signals, comprising:

• generating a first static output signal that holds its value for at least two successive clock cycles from a storage element;
• using a dynamic mux to select one of the following every clock cycle:
• either said first static output signal or a second static signal that holds its value for at least two successive clock cycles;
• receiving said first static output signal and said second static output signal at an NDL gate that further comprises a 1-of-N dynamic logic circuit implemented in FAST14 logic technology;
• and
• carrying said first static output signal using a transmission path coupled to said storage element, to said dynamic mux, and to said NDL gate, said transmission path is characterized by a multi-cycle path timing constraint that further comprises a pragma that is interpreted by a PATHMILL compiler to create statements that check the set-up and hold times of said first static signal relative to the rising edge or falling edge of user-specified clock signal pulses, said pragma is interpreted by a compiler to create statements that test the behavior of the apparatus during the clock signal pulses other than said user-specified clock signal pulses.