Hi-speed parallel configuration of programmable logic

A programmable logic integrated circuit comprising:

• n configuration bit inputs to input in parallel, n bits at a time, k configuration bits into the programmable logic integrated circuit, wherein n is an integer greater than 1, k is greater than n, and k is a number of configuration bits in a frame for configuring the programmable logic of the programmable logic integrated circuit;
• a data register to store at least the k configuration bits, wherein the data register is divided into n segments and each of the n configuration bit inputs is coupled to input configuration bits at one of n segmentation nodes;
• and
• a cyclic redundancy check circuit, coupled to a first the n configuration bit inputs, to perform a cyclic redundancy check on the configuration bits transferred through the first of the n configuration bit inputs.

A programmable logic integrated circuit comprising:

• n configuration bit inputs to input in parallel, n bits at a time, k configuration bits into the programmable logic integrated circuit, wherein n is an integer greater than 1, k is greater than n, and k is a number of configuration bits in a frame for configuring the programmable logic of the programmable logic integrated circuit;
• and
• a data register to store at least the k configuration bits, wherein the data register is divided into n segments and each of the n configuration bit inputs is coupled to input configuration bits at one of n segmentation nodes,
• wherein n is 8 and each of the segments does not have the same number of registers.

A programmable logic integrated circuit comprising:

• n configuration bit inputs to input in parallel, n bits at a time, k configuration bits into the programmable logic integrated circuit, wherein n is an integer greater than 1, k is greater than n, and k is a number of configuration bits in a frame for configuring the programmable logic of the programmable logic integrated circuit;
• a data register to store at least the k configuration bits, wherein the data register is divided into n segments and each of the n configuration bit inputs is coupled to input configuration bits at one of n segmentation nodes;
• a first multiplexer having a first input coupled to a second configuration bit input of the n configuration bit inputs, a second input coupled to a last register of a first segment of the data register, and a first multiplexer output coupled to a first register of a second segment of the data register;
• wherein the first register of the second segment is used to hold configuration data for a row L of the logic array blocks;
• and
• a second multiplexer having a first input coupled to the second configuration bit input of the n configuration bit inputs, a second input coupled to a last register to hold configuration data for row L of the logic array block, and a second multiplexer output coupled to a first register to hold configuration data for a row L+1 of the logic array blocks.

A programmable logic integrated circuit comprising:

• n configuration bit inputs to input in parallel, n bits at a time, k configuration bits into the programmable logic integrated circuit, wherein n is an integer greater than 1, k is greater than n, and k is a number of configuration bits in a frame for configuring the programmable logic of the programmable logic integrated circuit;
• and
• a data register to store at least the k configuration bits, wherein the data register is divided into n segments and each of the n configuration bit inputs is coupled to input configuration bits at one of n segmentation nodes,
• wherein the data register comprises registers to store m dummy data bits, and the dummy data bits will be supplied by software used to configure the programmable logic integrated circuit.

A method of configuring a programmable logic integrated circuit comprising:

• inputting a plurality of configuration bits into the programmable logic integrated circuit in parallel using a first input and a second input;
• loading the configuration bits provided by the first input starting at a first register of a first segment a data register, wherein the first segment comprises registers coupled together in a serial chain;
• and
• loading the configuration bits provided by the second input starting at a first register of a second segment the data register, wherein the second segment comprises registers coupled together in a serial chain.

A programmable integrated circuit comprising:

• a first data input;
• a second data input;
• a data register to hold configuration bits used to configure the programmable integrated circuit, wherein the data register comprises a fist segment comprising a plurality of registers coupled in a serial chain and a second segment comprising a plurality of registers coupled in a serial chain,
• wherein the first register of the first segment is coupled to the first data input;
• and
• a first multiplexer coupled to the second data input, a last register of the first segment, and a first register of the second segment.