US 6,714,043 B1Granted

Output buffer having programmable drive current and output voltage limits

AssigneeLattice Semiconductor Corporation

InventorBradley A. Sharpe-Geisler

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Abstract

An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The output buffer portion has an input connected to an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). Control power switches driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The CMOS buffer transistors are selectively enabled to control output drive current. Selectable pull-up and pull-down reference circuits provide references (VRFPU, VRFPPU, VRFPD and VRFPPD) to control the current of the buffer output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.

Claims13

Dependent claims

A buffer comprising:

an output signal node for receiving a signal to be provided to an external circuit;
an output pad for connecting to an external circuit;
an driver transistors having a source-drain path coupling the output pad to a first power supply terminal, and having a gate forming a first node;
and
a switching circuit driving the gate of one the driver transistor, each of the switching circuit comprising:
a voltage reference for providing a first voltage reference signal to a first voltage reference signal node, and for providing a second voltage reference signal to a second voltage reference signal node;
a first reference enabling transistor having a source-drain path coupling the first reference signal node to the first node, and having a gate;
a second reference controlled switch transistor having a source-drain path coupling a first power supply terminal to the first node and having a gate connected to the second voltage reference signal node;
a second reference enabling transistor having a source-drain path coupling the source-drain path of the first switch transistor to the first power supply terminal, and having a gate;
and
a logic gate connecting an output signal port to the gate of the first reference enabling transistor and the gate of the second reference enabling transistor.

8 more elements

A buffer comprising:

an output signal node for receiving a signal to be provided to an external circuit;
an output pad for connecting to an external circuit;
PMOS pull up transistors, each having a drain coupled to the output pad, a source coupled to a first power supply terminal, and having a gate forming a first node;
and
pull up switching circuits each driving the gate of one of the PMOS pull up transistors, each of the pull up switching circuits comprising:
a voltage reference for providing pull up voltage references for supplying a first pull-up reference signal to a first pull-up reference signal node, and for providing a second pull-up reference signal to a second pull-up reference signal node;
a NMOS gating transistor having a source-drain path coupling the a first pull-up reference signal node to the first node, and having a gate;
a first pull up switch transistor having a source-drain path coupling a first power supply terminal to the first node and having a gate connected to the second pull-up voltage reference signal node;
a PMOS control transistor having a source-drain path coupling the source-drain path of the first pull up switch transistor to the first power supply terminal, and having a gate;
and
a logic gate connecting an output signal port (D) to the gate of the NMOS gating transistor and the PMOS control transistor.

8 more elements

A buffer comprising an output buffer portion comprising:

an output signal node for receiving a signal to be provided to an external circuit;
an output pad for connecting to an external circuit;
NMOS pull down transistors, each having a drain coupled to the output pad, a source coupled to a first power supply terminal, and having a gate forming a first node;
and
a plurality of pull down switching circuits, each driving the gate of one of the NMOS pull down transistors, each of the pull down switching circuits comprising:
a voltage reference for providing pull down voltage references for supplying a first pulldown reference signal to a first pull-down reference signal node, and for providing a second pull-up reference signal to a second pull-down reference signal node;
a PMOS gating transistor having a source-drain path coupling the first pull-down reference signal node to the first node, and having a gate;
a PMOS pull down switch transistor having a source-drain path coupling a first power supply terminal to the first node, and having a gate connected to the second pull-down reference signal node;
and
a first logic gate connecting an output signal port to the gate of the PMOS gating transistor.

7 more elements

Dependencies are inferred from the claim text.