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US 6,714,041 B1Granted
Programming on-the-fly (OTF)
AssigneeXilinx, Inc.
InventorsRoy D. Darling, Schuyler E. Shimanek, Thomas J. Davies, Jr.
Life of this patent
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AssigneeXilinx, Inc.
InventorsRoy D. Darling, Schuyler E. Shimanek, Thomas J. Davies, Jr.
Estimating the term…
A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data while the CPLD is operating in a first configuration. This relatively time-consuming operation has no effect on CPLD operation since only the SRAM array controls the configuration of the CPLD. At a desired point in time, the new configuration data from the EEPROM array can be loaded into the SRAM array to reconfigure the CPLD. Because this loading of configuration data into the SRAM array takes only microseconds to perform, normal system operation effectively proceeds without interruption. A CPLD can include multiple EEPROM arrays, each storing a different set of configuration data, thereby allowing the CPLD to rapidly switch between various configurations by loading the configuration data from different EEPROM arrays into the SRAM array.
A method for reconfiguring a complex programmable logic device (CPLD) in an electronic system, the CPLD comprising an electrically-erasable programmable read-only memory (EEPROM) array, a static random access memory (SRAM) array, a control circuit for loading data from the EEPROM array into the SRAM array, and a plurality of macrocells connected by a programmable interconnect matrix, the method comprising:
A computer readable medium storing an instruction for a complex programmable logic device (CPLD), the CPLD comprising a first electrically-erasable programmable read-only memory (EEPROM) array, a static random access memory (SRAM) array, a control circuit configured to load data from the first EEPROM array into the SRAM array, a plurality of macrocells connected by a programmable interconnect matrix, and a plurality of output terminals coupled to the plurality of macrocells, wherein a first set of configuration data stored in the SRAM array configures the plurality of macrocells and the programmable interconnect matrix to place the CPLD in a first configuration, the instruction comprising a first command for programming the first EEPROM array with a second set of configuration data while the CPLD is operating in the first configuration.
A complex programmable logic device (CPLD) comprising a first EEPROM array for storing a first set of configuration data, a second EEPROM array for storing a second set of configuration data, an SRAM array, a control circuit configured to load data from the first EEPROM array or the second EEPROM array into the SRAM array, a plurality of macrocells connected by a programmable interconnect matrix, and a plurality of output terminals coupled to the plurality of macrocells, wherein the SRAM array configures the plurality of macrocells and the programmable interconnect matrix to configure the CPLD.
A method for reconfiguring a complex programmable logic device (CPLD) in an electronic system, the CPLD comprising a first electrically-erasable programmable read-only memory (EEPROM) array, a second EEPROM array, a static random access memory (SRAM array), a control circuit for loading data from the first EEPROM array or the second EEPROM array into the SRAM array, and a plurality of macrocells connected by a programmable interconnect matrix, wherein a first set of configuration data in stored in the SRAM array configures the plurality of macrocells and the programmable interconnect matrix to place the CPLD in a first configuration, the method comprising programming the first EEPROM array and the second EEPROM array with a second set of configuration data and a third set of configuration data, respectively, while operating the electronic system with the CPLD in the first configuration.
Dependencies are inferred from the claim text.