Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation

A method for reducing a propagation delay of a signal across a transmission line, comprising:

• inserting at least one repeater along said transmission line, said at least one repeater comprising a first PFET and a first NFET, said first PFET having a first PFET source, a first PFET gate, and a first PFET drain, and said first NFET having a first NFET source, a first NFET gate, and a first NFET drain, said inserting said at least one repeater comprising coupling said first PFET source to a high voltage source, coupling said first PFET gate to a repeater input, coupling said first PFET drain to a repeater output, coupling said first NFET source to a low voltage source, coupling said first NFET gate to said repeater input, and coupling said first NFET drain to said repeater output;
• and
• terminating said at least one repeater with at least one corresponding termination circuit in very close proximity to said repeater input of said at least one repeater, said at least one corresponding termination circuit comprising a second PFET and a second NFET, said second PFET having a second PFET source, a second PFET gate, and a second PFET drain, and said second NFET having a second NFET source, a second NFET gate, and a second NFET drain, said terminating said at least one repeater comprising coupling said second PFET source to a high voltage source, coupling said second PFET gate to a repeater input, coupling said second PFET drain to said repeater input, coupling said second NFET source to a low voltage source, coupling said second NFET gate to said repeater input, and coupling said second NFET drain to said repeater input;
• wherein first NFET and said second NFET are ratioed to vary similarly under process, voltage, and temperature (PVT) variation, and said first PFET and said second PFET are ratioed to vary similarly under process, voltage, and temperature (PVT) variation.