Apparatus for controlling input termination of semiconductor memory device and method for the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByong-Kwon Lee, Kwang-Jin Lee
Life of this patent
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Abstract
An apparatus and method for controlling an input termination of a semiconductor memory device that easily detect and analyze defects, functions and reliability of the device by controlling operations of the input termination. The apparatus comprises an input termination circuit for matching an impedance of a transmission line, a control circuit for processing test commands and outputting control signals in response to said processing, and a switching circuit for selectively turning on/off the input termination circuit in response to the control signals output from the control circuit.
Claims21
An apparatus for controlling an input termination of a semiconductor device, comprising:
- an input termination circuit for matching an impedance of a transmission line;
- a test circuit for processing test commands for testing a semiconductor device and outputting control signals in response to said processing of said test commands;
- and
- a switching circuit for selectively turning on/off the input termination circuit in response to the control signals output from the test circuit.
An apparatus for controlling an input termination of a semiconductor memory device, comprising:
- a pad for receiving a first control signal to control an input termination circuit;
- a switching circuit that selectively turns on/off the input termination circuit in response to the first control signal;
- a test circuit for receiving test commands and outputting a second control signal in response to the test commands;
- and
- an OR gate having input terminals connected to the output of the test circuit and the pad, for outputting a third control signal in response to the first and second control signals to selectively turn on/off the input termination circuit in response to the third control signal.
A semiconductor device, comprising:
- an input termination circuit for matching an impedance of a transmission line connected to the input of a semiconductor memory device;
- a test circuit for processing test commands for testing the semiconductor memory device and outputting a control signal in response to said processing of said test commands;
- a pad for receiving the control signal that one of activates and deactivates the input termination circuit, wherein the input termination circuit is deactivated to prevent leakage current from flowing in the input termination circuit during a testing procedure.
A method for controlling an input termination of a semiconductor memory device, comprising the steps of:
- in response to a test command signal, outputting a control signal to deactivate an input termination, when a testing procedure is to be performed for the semiconductor memory device;
- and
- deactivating a plurality of switches to electrically isolate the input termination, and thus prevent leakage current from flowing in the input termination during a test procedure.
Dependencies are inferred from the claim text.