System and method for measuring fault coverage in an integrated circuit
AssigneeHewlett-Packard Development Company, L.P.
InventorJeffrey Paul Witte
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Abstract
A system and method for measuring fault coverage in an integrated circuit (IC) using a stuck-at fault model is disclosed. The system includes a Device Under Test (DUT) assembly having the IC that includes at least one node, a probe and a test pattern generator and interface system. The DUT's nodes are operable to be stimulated to a stuck-at fault state when stimulated by a certain frequency of electromagnetic (EM) radiation, which fault state is operable to be discovered by a suitable test vector set.
Claims21
A system for measuring fault coverage in an integrated circuit (IC), comprising:
- a Device Under Test (DUT) assembly including said IC, wherein said IC includes at least one node selected from a node list associated with said IC such that said at least one node is operable to be stimulated to a stuck-at fault condition by a certain frequency of electromagnetic (EM) radiation;
- a probe operable to stimulate said DUT assembly with said frequency of EM radiation;
- and
- a test pattern generator and interface system interfacing with said DUT assembly, said test pattern generator and interface system operating to apply a test vector to said DUT assembly and receive a corresponding response, wherein said corresponding response is indicative of a fault coverage measurement.
A method for measuring fault coverage in an integrated circuit (IC), comprising the steps of:
- determining a master mode list for said IC;
- creating a stuck-at fault condition at a select number of nodes associated with said IC;
- applying a test vector set to said IC upon creating said stuck-at fault condition;
- comparing said IC's output against expected results associated with said test vector set;
- and
- determining fault coverage as a percentage of said stuck-at fault conditions detected by said test vector set.
A system for measuring fault coverage in an integrated circuit (IC), comprising:
- means for determining a master node list for said IC;
- means for creating a stuck-at fault condition at a select number of nodes associated with said IC;
- means for applying a test vector set to said IC upon creating said stuck-at fault condition;
- means for comparing said IC's output against expected results associated with said test vector set;
- and
- means for determining fault coverage as a percentage of said stuck-at fault conditions detected by said test vector set.
Dependencies are inferred from the claim text.