Power saving integrated circuit and method of controlling the same

A power saving integrated circuit having a power saving mode function, comprising:

• a power supply which supplies a power supply voltage;
• an operating circuit having a memory which stores an operating condition of the operating circuit, wherein a supply of the power supply voltage to the operating circuit is interrupted when the integrated circuit is in a power saving mode, and wherein the operating condition includes a reset delay period which is set in accordance with an operating voltage level of the operating circuit and a clock frequency which is correlated with the reset delay period;
• a switching circuit which switches the supply of the power supply voltage to the operating circuit;
• a first register which receives and stores a signal indicative of the reset delay period;
• a second register which receives and stores a signal indicative of the clock frequency;
• a counter which continues to output a reset signal to the operating circuit in accordance with the reset delay period;
• and
• a dividing counter which divides a clock signal and outputs a divided clock signal to the operating circuit in accordance with the clock frequency.

A method of controlling a power saving integrated circuit having a normal active mode and a power saving mode, comprising:

• detecting a first signal which shows a transition from the normal active mode to the power saving mode;
• interrupting supply of a power supply voltage to an operating circuit in the integrated circuit responsive to said detecting a first signal;
• storing an operating condition signal which indicates an operating condition of the operating circuit;
• outputting a reset signal to the operating circuit in accordance with the stored operating condition signal;
• starting a reset delay period in response to a release signal, which indicates release of the interruption of the supply of the power supply voltage, the reset delay period being set in accordance with the operating condition signal;
• and
• stopping the output of the reset signal after a termination of the reset delay period.

A method of controlling a power saving integrated circuit having a normal active mode and a power saving mode, comprising:

• detecting a first signal which shows a transition from the normal active mode to the power saving mode;
• interrupting supply of a power supply voltage to an operating circuit in the integrated circuit responsive to said detecting a first signal;
• storing a reset delay period which is set in accordance with an operating voltage level of the operating circuit;
• storing a clock frequency which is in correlation with the reset delay period;
• outputting a reset signal to the operating circuit in accordance with the stored reset delay period;
• dividing a clock signal and outputting a divided clock signal to the operating circuit in accordance with the stored clock frequency;
• releasing the power saving mode in response to a release signal which indicates a time to release the interruption of the supply of the power supply voltage;
• and
• interrupting the output of the reset signal after a termination of the reset delay period.