Surface mount solder method and apparatus for decoupling capacitance and process of making
AssigneeIntel Corporation
InventorsDamion T. Searls, Weston C. Roth, James Daniel Jackson
Life of this patent
Estimating the term…
Abstract
A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.
Claims25
A decoupling capacitor system comprising:
- a substrate including a substrate first pad and a substrate second pad;
- an electrical first bump including a bottom end and a top end, wherein the bottom end is adhered to the first pad;
- an electrical second bump including a bottom end and a top end, wherein the bottom end is adhered to the second pad;
- a first capacitor disposed above the substrate and substantially contiguous to the electrical first bump;
- a top structure disposed at the electrical first bump top end, wherein the top structure is in electrical communication with the first capacitor and is selected from an electronic component, an interposer, a socket, and combinations thereof;
- and
- a current loop that originates in the first capacitor, that passes through the top structure, and that terminates in the first capacitor, wherein the current loop is selected from a simple current loop and a simple deflected current loop.
An apparatus comprising:
- a first decoupling capacitor;
- an electronic component;
- and
- a current loop that originates in the decoupling capacitor, that passes through the electronic component, and that terminates in the first decoupling capacitor, wherein the current loop is selected from a simple current loop and a simple deflected current loop.
A current loop in a decoupling capacitor system comprising:
- a capacitor including a power terminal and a ground terminal;
- a component disposed above the capacitor;
- a loop origin in the power terminal;
- a loop first direction out of the power terminal and toward the component;
- a loop second direction within the component;
- a loop third direction out of the component and toward the ground terminal;
- and
- a loop terminus in the ground terminal, wherein the loop is selected from a simple loop and a simple deflected loop.
An article comprising:
- a substrate including a power plane and a ground plane;
- a Vcc first pad and a Vss second pad disposed above the substrate and in respective electrical communication with the power plane and the ground plane;
- a Vcc electrical first bump disposed above the Vcc first pad;
- a Vss electrical second bump disposed above the Vss second pad;
- a capacitor including a Vcc terminal and a Vss terminal disposed between the electrical first bump and the electrical second bump, wherein the Vcc terminal is disposed above the Vcc first pad and the Vss terminal is disposed above the Vss second pad;
- a top structure coupled to the Vcc electrical first bump and the Vss electrical second bump;
- and
- a current loop that originates in the capacitor, that passes through the top structure, and that terminates in the capacitor, wherein the current loop is selected from a simple current loop and a simple deflected current loop.
A decoupling capacitor system comprising:
- a substrate including a substrate first pad and a substrate second pad;
- an electrical first bump including a bottom end and a top end, wherein the bottom end is adhered to the first pad;
- an electrical second bump including a bottom end and a top end, wherein the bottom end is adhered to the second pad;
- a first capacitor disposed above the substrate;
- a top structure disposed at the electrical first bump top end, wherein the top structure is in electrical communication with the first capacitor and is selected from an electronic component, an interposer, a socket, and combinations thereof;
- at least one capacitor in addition to the first capacitor, wherein the at least one capacitor in addition to the first capacitor is disposed, selected from above and on the substrate, and on the top structure;
- and
- a current loop that originates in the first capacitor, that passes through the top structure, and that terminates in the first capacitor, wherein the current loop is selected from a simple current loop and a simple deflected current loop.
Dependencies are inferred from the claim text.