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US 6,713,869 B2Granted
Wiring pattern of semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsTakeshi Kusakabe, Toshitsune Iijima
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Abstract
A semiconductor package of this invention comprises an electrode pad arranged on a semiconductor chip, a bonding wire, an end of which is coupled to the electrode pad, and a connection pad arranged parallel to a direction of arrangement of the bonding wire, to which another end of the bonding wire is coupled, and a pitch of the connection pad is wider than that of the electrode pad.
Claims6
A semiconductor packages, comprising:
- a substrate including an opening;
- a wiring pattern including plurality of wire portions arranged on said substrate;
- connection pads coupled near the opening to an end of said wire portions;
- a semiconductor chip including plurality of electrode pads disposed in a line, and arranged on said substrate so that said electrode pads expose from said opening;
- and
- plurality of bonding wires coupled to said connection pads and said electrode pads, wherein
- said connection pads are disposed at a non-right angle with respect to the line and are coupled to said bonding wires so that a direction that said connection pads align are substantially parallel to a direction that said bonding wires aligns, and a spacing interval between the bonding wires is narrower as the bonding wires approach the electrode pads.
4 more elements
Dependencies are inferred from the claim text.