Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package

A fabrication method of a stacked multi-chip semiconductor package, comprising the steps of:

• preparing a chip carrier having a first surface and a second surface opposed to the first surface, wherein at least an opening is formed through the chip carrier;
• applying an adhesive tape on the second surface of the chip carrier and over the opening, allowing the adhesive tape to be partly exposed to the opening;
• mounting at least a first chip within the opening of the chip carrier, and attaching the first chip to the adhesive tape, the first chip being electrically connected to the chip carrier, wherein the first chip has a thickness not larger than the thickness of the chip carrier between the first and second surface thereon;
• forming a first encapsulant on the first surface of the chip carrier, the first encapsulant filling into the opening of the chip carrier for encapsulating the first chip;
• removing the adhesive tape from the second surface of the chip carrier;
• forming a second encapsulant on the second surface of the chip carrier at area outside the opening to encompass a cavity;
• mounting at least a second chip within the cavity on the second surface of the chip carrier and over the opening, and stacking the second chip on the first chip via an adhesive, the second chip being electrically connected to the chip carrier, wherein the second chip has a thickness larger than the thickness of the first chip and a width larger than the width of the opening in the chip carrier such that the second chip simultaneously contacts both the first chip and the chip carrier;
• and
• attaching a lid to the second encapsulant for covering the cavity.