Dual die memory

A method of providing a dual-die, double-sized, back-to-back integrated-circuit chip assembly, comprising the steps of:

• providing a first and a second integrated-circuit chip, each having one or more electrically reversible wire-bonding-pads;
• centrally mounting the first and the second integrated-circuit chips back-to-back within a lead frame having inwardly-extending bonding fingers with one of said chips having its wire-bonding-pads electrically reversed such that the pads for similar functions are located near each other for wire-bonding to a common bonding finger of said lead frame;
• and for each integrated-circuit chip:
• connecting an input signal terminal of a first gate circuit to a first wire-bonding-pad, connecting an output signal terminal of the first gate circuit to a first common signal line, and receiving a standard wire-bonding configuration control signal at a control terminal of the first gate circuit, which control signal operates the first gate circuit to provide a standard pattern for the first wire-bonding-pad, which standard pattern connects the first wire-bonding-pad to a first common signal line to thereby provide a first input LOGIC signal to the first common signal line on said integrated-circuit chip;
• connecting an input signal terminal of a second gate circuit to the first wire-bonding-pad, connecting an output signal terminal of the second gate circuit to a second common signal line, and receiving a non-standard, reversed wire-bonding configuration control signal at a control terminal of the second gate circuit, which control signal operates the second gate circuit to alternatively provide a non-standard, reversed pattern for the first wire-bonding-pad, which non-standard, reversed pattern connects the first wire-bonding-pad to a second common signal line to thereby alternatively provide the first input LOGIC signal to the second common signal line on said integrated-circuit chip;
• connecting an input signal terminal of a third gate circuit to a second wire-bonding-pad, connecting an output signal terminal of the third gate circuit to a second common signal line, and receiving the standard wire-bonding configuration control signal at a control terminal of the third gate circuit, which control signal operates the third gate circuit to provide a standard pattern for the second wire-bonding-pad, which standard pattern connects the second wire-bonding-pad to a second common signal line to thereby provide a second input LOGIC signal to the second common signal line on said integrated-circuit chip;
• connecting an input signal terminal of a fourth gate circuit to the second wire-bonding-pad, connecting an output signal terminal of the fourth gate circuit to the second common signal line, and receiving the non-standard, reversed wire-bonding configuration control signal at a control terminal of the fourth gate circuit, which control signal operates the fourth gate circuit to alternatively provide a non-standard, reversed pattern for the second wire-bonding-pad, which non-standard, reversed pattern connects the second wire-bonding-pad to the first common signal line to thereby alternatively provide the second input LOGIC signal to the first common signal line on said integrated-circuit chip;
• wherein the first gate circuit and the third gate circuit are controlled by the standard-bonding-pad control signal to provide a predetermined standard bonding-pad configuration for the integrated-circuit chip, which standard bonding-pad configuration connects the first wire-bonding input pad to the first common signal line on the integrated-circuit chip and which standard bonding-pad configuration also connects the second wire-bonding-pad to the second common signal line;
• and
• wherein the second gate circuit and the fourth gate circuit are controlled by the reverse-bonding-pad control signal to provide a predetermined alternative reversed bonding-pad configuration for the integrated-circuit chip, which alternative reversed bonding-pad configuration connects the first wire-bonding-pad to the second common signal line and which alternative reversed bonding-pad configuration also connects the second wire-bonding-pad to first common signal line.

A method of providing a dual-die, double-sized, back-to-back, wire-bonded integrated-circuit chip assembly, comprising:

• providing a first chip having one or more reversible wire-bonding-pads;
• and
• providing a second chip having one or more reversible wire-bonding-pads;
• centrally mounting back-to-back the first and second integrated-circuit chips within a lead frame having inwardly-extending bonding fingers with one of said chips having its wire-bonding-pads electrically reversed such that the pads for similar functions are located near each other for wire-bonding to a common bonding finger of said lead frame;
• applying an external voltage to a bonding-option wire-bonding-pad adapted to indicate whether the integrated-circuit chip is to provide a standard pattern for the reversible wire-bonding-pads, or alternatively, whether the integrated-circuit chip is to provide a reversed path for the reversible wire-bonding-pads;
• and
• sensing the voltage applied to the bonding-option wire-bonding-pad for alternatively generating either a standard NRO gate control signal or a non-standard, reversed RO gate control signal from the voltage state of the bonding-option wire-bonding-pad.