Electronic package with offset reference plane cutout
AssigneeApplied Micro Circuits Corporation
InventorsSiamak Fazelpour, Michel Fleury, Mark Patterson
Life of this patent
Estimating the term…
Abstract
An electronic package, such as a ball grid array (“BGA”) package, includes a high speed signal trace formed at a conductive layer and a corresponding reference plane formed at another conductive layer. The reference plane includes a cutout region formed therein; the cutout region is positioned over the signal solder ball to which the high speed signal trace is coupled. The lateral center point of the cutout region is offset relative to the lateral center point of the signal solder ball. The offset configuration reduces the capacitance between the signal solder ball and the reference plane and improves the high frequency transmission characteristics of the electronic package.
Claims18
An electronic package comprising:
- a multilayer substrate having a mounting surface and one or more conductive layers;
- a signal connection terminal attached to said mounting surface of said multilayer substrate and coupled to a high speed signal trace formed at one of said conductive layers, said signal connection terminal having a first lateral center point;
- and
- a reference plane formed at one of said conductive layers, said reference plane having a cutout region formed therein, said cutout region having a second lateral center point that is laterally offset relative to said first lateral center point.
An electronic package comprising:
- a multilayer substrate having one or more conductive layers, including a conductive mounting surface layer;
- a capture pad formed at said conductive mounting surface layer and coupled to a high speed signal trace formed at one of said conductive layers, said capture pad having a first lateral center point;
- and
- a reference plane formed at one of said conductive layers, said reference plane having a cutout region formed therein, said cutout region having a second lateral center point that is laterally offset relative to said first lateral center point.
An electronic package comprising:
- a multilayer substrate having one or more conductive layers;
- a high speed signal trace formed at a first conductive layer of said multilayer substrate;
- a capture pad formed at a second conductive layer of said multilayer substrate and coupled to said high speed signal trace, the projection of said capture pad onto said first conductive layer intersecting said high speed signal trace at an edge location;
- and
- a reference plane formed at one of said conductive layers, said reference plane having a cutout region formed therein, the projection of said cutout region onto said first conductive layer being biased away from said edge location.
Dependencies are inferred from the claim text.