Split gate flash with strong source side injection and method of fabrication thereof

A new split gate memory cell structure for improved programming efficiency comprising:

• a silicon region extending to the surface of a substrate;
• parallel active regions on said silicon region defined by isolation regions;
• source/drain regions in said silicon region situated at regular intervals along the active regions, with silicon pedestals over the source/drain regions;
• first insulator regions alternating with silicon pedestals along the active regions, said first insulator regions and silicon pedestals being directly over the silicon region;
• floating gate towers, disposed over the first insulator regions, composed of floating gates that are separated from the silicon region by the first insulator regions, second insulating layers separating the floating gates from top gates that run perpendicular to the active regions and third insulator layers disposed over the top gates;
• a first sidewall insulating layer covering the sidewalls of each of said floating gate towers separating the floating gates from the silicon pedestals;
• a second sidewall insulating layer disposed over said first sidewall insulating layer, ending at the silicon pedestals;
• source/drain connecting towers disposed over silicon pedestals composed of source/drain connecting regions which run perpendicular to the active regions, are in direct electrical contact with the silicon pedestals, are separated from the floating gate towers by the combined thickness of the first sidewall insulating layers and the second sidewall insulating layers, and that are covered by a fourth insulating layer that also partially covers the tops of adjoining floating gate towers;
• a multiplicity of selected gate towers between pairs of source/drain towers, each selected gate tower disposed over a silicon pedestal and is composed of a selected gate separated from the silicon pedestal by a fifth insulator layer;
• a connection region providing contact to the selected gates.

A method to fabricate a new split gate memory cell structure for improved programming efficiency comprising:

• providing a silicon region extending to the surface of a substrate;
• defining parallel active regions on said silicon region by forming isolation regions that surround said active regions;
• forming a first insulator layer over said active regions;
• forming a first conductor layer over said first insulator layer and patterning said first conductor layer to achieve parallel strips that are parallel to and disposed over said active regions;
• forming successively three blanket layers, a second insulating layer, a second conductive layer, and a third nitride layer and patterning said three blanket layers to form parallel strips three layers deep perpendicular to the active regions and removing any of said first conductor layer that is not under said three layer deep strips;
• depositing a first sidewall insulator layer and etching said first sidewall insulator layer to form first sidewall spacers;
• forming silicon pedestals over exposed segments of the active regions and bounded on the sides by the first sidewall spacers;
• depositing a second sidewall insulator layer;
• etching said second sidewall insulator layer to form second sidewall spacers;
• forming a fourth insulator layer over the silicon pedestals;
• forming source/drain connection regions and selected gate regions where there can be a multiplicity n of selected gate regions between pairs of source/drain regions;
• and
• where the source/drain regions are formed by performing source/drain implants, removing the fourth insulating layer from over the silicon pedestals, forming a third conducting layer in the form of strips perpendicular to the active regions that almost fill the region above silicon pedestals bounded by second sidewall spacers and forming a fifth insulating layer that is disposed over the third conducting layer and also extends over neighboring portions of third insulator layers;
• and where the selected gate regions are formed by forming a fourth conducting layer in the form of strips perpendicular to the active regions that almost fill the region above silicon pedestals bounded by second sidewall spacers;
• forming a fifth conducting layer in the farm of strips disposed above and parallel to the active regions.