Dual bit memory device with isolated polysilicon floating gates
AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited
InventorsJusuke Ogura, Kazuhiro Kurihara, Masaru Yano, Hideki Komori, Tuan Pham, Angela Hui
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Abstract
The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.
Claims17
A semiconductor memory device comprising:
- an array of two-bit floating gate transistors on a silicon wafer substrate, said array comprising a plurality of isolation openings;
- each of said two-bit floating gate transistors having polysilicon floating gates between parallel rows of bit-line oxide, wherein a bit-line is between and parallel said parallel rows of bit-line oxide, said bit line comprising a plurality of doped regions disposed beneath said floating gates;
- each of said two-bit floating gate transistors having an isolation opening of said plurality of isolation openings between said parallel rows of bit-line oxide that divide said floating gates;
- and
- a polysilicon control gate overlying said floating gates and a continuous ONO layer disposed therebetween and above said bit-line oxide.
A semiconductor memory device comprising:
- an array of two-bit floating gate transistors on a silicon wafer substrate, said array comprising a plurality of isolation openings;
- each of said two-bit floating gate transistors having one pair of isolated polysilicon floating gates adjacent parallel rows of bit-line oxide, one said of said floating gates for each bit, wherein a bit-line is between and parallel said parallel rows of bit-line oxide, said bit line comprising a plurality of doped regions disposed beneath said floating gates;
- each of said two-bit floating gate transistors having an isolation opening of said plurality of isolation openings between said parallel rows of bit-line oxide that divide said floating gates;
- and
- a polysilicon control gate overlying said floating gates and a continuous ONO layer disposed therebetween and above said bit-line oxide.
A semiconductor memory device comprising:
- an array of two-bit floating gate transistors on a silicon wafer substrate, said array comprising a plurality of isolation openings;
- each of said two-bit floating gate transistors having one pair of isolated polysilicon floating gates adjacent parallel rows of bit-line oxide, one said of said floating gates for each bit, wherein a bit-line is between and parallel said parallel rows of bit-line oxide, said bit line comprising a plurality of doped regions disposed beneath said floating gates;
- a silicon dioxide tunnel layer disposed between said floating gates and said silicon wafer substrate;
- each of said two-bit floating gate transistors having an isolation opening of said plurality of isolation openings between said parallel rows of bit-line oxide that divide said floating gates;
- a continuous ONO layer overlying said floating gates and above said bit-line oxide, and
- a polysilicon control gate overlying said continuous ONO layer.
Dependencies are inferred from the claim text.