Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures

A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises:

• a) forming one of one or more layers of dielectric material, including a layer of low k dielectric material, over at least raised portions of the underlying integrated circuit structure;
• b) forming a planarizable layer of dielectric material over said one or more layers of dielectric material including said layer of low k dielectric material;
• c) forming a removable mask over said planarizable layer of dielectric material, said mask having openings formed therein to expose a portion of the upper surface of said planarizable layer of dielectric material over at least some of said raised portions of said integrated circuit structure;
• d) etching said exposed portions of said planarizable layer of dielectric material through such openings in said mask to remove a portion, but not all of:
• i) said planarizable layer of dielectric material;
• and
• ii) said one or more dielectric layers;
• formed over said raised portions of said underlying integrated circuit structure to reduce the overall volume of said planarizable layer of dielectric material overlying said raised portions of said integrated circuit structure;
• e) removing said mask;
• and
• f) planarizing said planarizable layer of dielectric layer;
• whereby removal, before a planarization step, of a portion of the overall volume of said planarizable layer of dielectric material over said raised portions of said integrated circuit structure reduces the planarization time and thereby inhibits cracking of said layer of low k dielectric material layer.

A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises:

• a) forming one or more layers of dielectric material, including a layer of low k dielectric material, over an underlying integrated circuit structure having raised portions thereon;
• b) forming a planarizable layer of dielectric material over said one or more dielectric layers;
• c) forming a removable mask over said planarizable layer of dielectric material, said mask having openings formed therein in registry with at least some of said raised portions of said underlying integrated circuit structure to expose portions of the upper surface of said planarizable layer of dielectric material over at least some of said raised portions of said integrated circuit structure;
• d) etching said exposed portions of said planarizable layer of dielectric material through such openings in said mask to remove at least a portion of said planarizable layer of dielectric material formed over said raised portions of said underlying integrated circuit structure, to reduce the overall volume of said one or more dielectric layers overlying said raised portions of said underlying integrated circuit structure;
• e) removing said mask;
• and
• f) planarizing said planarizable layer of dielectric layer;
• whereby removal, before a planarization step, of at least a portion of the overall volume of said planarizable layer of dielectric material over said one or more dielectric layers over said raised portions of said integrated circuit structure inhibits cracking of said layer of low k dielectric material.

A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises:

• a) forming a thin base layer of dielectric material over at least raised portions of said integrated circuit structure;
• b) forming a layer of low k carbon-doped silicon oxide dielectric material over said base layer of dielectric material;
• c) forming a thin capping layer of dielectric material over said layer of low k dielectric material;
• d) forming a removable mask over said capping layer of dielectric material;
• said mask having openings formed therein in registry with peaks of at least some of said raised portions of said underlying integrated circuit structure to expose at least a portion of the upper surface of said capping layer of dielectric layers over at least some of said raised portions of said integrated circuit structure;
• e) etching exposed portions of said one or more dielectric layers through such openings in the mask to remove a portion, but not all, of said capping layer of dielectric material and underlying layer of low k carbon-doped silicon oxide dielectric material formed over said raised portions of said underlying integrated circuit structure, to reduce the overall volume of said dielectric layers overlying said raised portions of said underlying integrated circuit structure;
• f) removing said mask;
• g) forming a planarizable layer of dielectric material over said etched capping layer of dielectric material and said layer of low k dielectric layers;
• and
• h) planarizing said planarizable layer of dielectric layer;
• whereby removal, before a planarization step, of a portion of the overall volume of said capping layer of dielectric material and said layer of low k dielectric material over said raised portions of said integrated circuit structure inhibits cracking of said layer of low k dielectric material.