System for reducing segregation and diffusion of halo implants into highly doped regions

A method of fabricating a transistor, comprising the steps of:

• forming a gate dielectric over a semiconductor body;
• forming a gate electrode over the gate dielectric;
• forming an implant blocking spacer adjacent sidewalls of the gate electrode;
• forming a first doped region of a first conductivity type in the semiconductor body adjacent the implant blocking spacer;
• forming a halo region of a second conductivity type in the semiconductor body at least partially under the implant blocking spacer to form a halo in the semiconductor body;
• selecting a fluorine dose and energy to tailor one or more characteristics of the transistor wherein the one or more characteristics of the transistor includes bottom wall and near edge capacitance;
• implanting fluorine into the halo region at the selected dose and energy;
• forming a sidewall spacer adjacent to the implant blocking spacer;
• and
• forming deep source/drain region in the semiconductor body aligned to the sidewall spacer.