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US 6,713,357 B1Granted
Method to reduce parasitic capacitance of MOS transistors
AssigneeAdvanced Micro Devices, Inc.
InventorsHai Hong Wang, Mark W. Michael, Wen-Jie Qi, William G. En, John G. Pellerin
Life of this patent
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Abstract
The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.
Claims16
A method of manufacturing a semiconductor device having reduced parasitic capacitance, comprising sequential steps of:
- (a) providing a semiconductor substrate including a surface with at least one MOS transistor structure therein or thereon, including a spaced-apart pair of shallow depth source and drain regions and an electrically conductive gate electrode having first and second opposing side surfaces and a top surface;
- (b) forming a thin, L-shaped sidewall spacer of a high dielectric constant (high-k) insulator material on each of said first and second opposing side surfaces of said gate electrode, each said thin, L-shaped sidewall spacer having a vertical portion extending for about 1,000-1,500 Å along e a respective side surface of said gate electrode to said top surface of said gate electrode and a horizontal portion extending on said substrate surface for a distance of about 500-800Å;
- and
- (c) forming a layer of a low dielectric constant (low-k) insulator material over at least said vertical and horizontal portions of each of said thin, L-shaped sidewall spacers, whereby parasitic capacitance between said gate electrode and each of said source and drain regions is reduced.
1 more element
A method of manufacturing a semiconductor device having reduced parasitic capacitance, comprising sequential steps of:
- (a) providing a semiconductor substrate of a first conductivity type having a surface with at least one MOS transistor structure therein or thereon, including:
- (i) a thin gate insulator layer in overlying contact with at least a portion of said substrate surface;
- (ii) an electrically conductive gate electrode in overlying contact with said thin gate insulator layer, said gate electrode comprising first and second opposing side surfaces and a top surface;
- (iii) a pair of spaced-apart, shallow-depth, lightly-doped source and drain regions, each of said source and drain regions extending in said substrate to just beneath a respective proximal edge of said gate electrode;
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- (iv) a thin conformal liner layer in overlying contact with said substrate surface and said first and second opposing side surfaces and said top surface of said gate electrode;
- (b) forming a thin, L-shaped sidewall spacer of a high dielectric constant (high-k) insulator material on each of said first and second opposing side surfaces of said gate electrode by sequential steps of:
- (b1) forming a relatively thin, conformal layer of said high-k insulator material extending over said substrate surface and said first and second opposing side surfaces and said top surface of said gate electrode;
- (b2) forming a relatively thick, conformal layer of an insulator material extending over said relatively thin, conformal layer of said high-k insulator material;
- (b3) selectively removing portions of said relatively thick, conformal layer of insulator material which overlie portions of said relatively thin layer of high k insulator material on said substrate surface and which overlie said top surface of said gate electrode, thereby forming a pair of insulative spacers each in contact with respective vertically and horizontally extending portions of said relatively thin layer of high-k insulator material;
- (b4) selectively removing portions of said relatively thin layer of high-k insulator material which overlie said top surface of said gate electrode and which extend on said substrate surface past said insulative spacers;
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- (b5) selectively removing said pair of insulative spacers, each said thin. L-shaped sidewall spacer having a vertical portion extending on a respective side surface of said gate electrode to said top surface of said gate electrode and a horizontal portion extending on said substrate surface for a selected distance;
- and
- (c) forming a layer of a low dielectric constant (low-k) insulator material over at least said vertical and horizontal portions of each of said thin, L-shaped sidewall spacers, whereby parasitic capacitance between said gate electrode and each of said source and drain regions is reduced.
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Dependencies are inferred from the claim text.