Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench

A semiconductor memory device fabrication method, comprising the steps of:

• preparing a semiconductor substrate;
• forming a plurality of first impurity regions in the semiconductor substrate for serving as source regions and drain regions of a first access transistor, a second access transistor, a first drive transistor and a second drive transistor;
• forming an insulation layer on the semiconductor substrate;
• forming a first contact hole in one of the plurality of the first impurity regions serving as the drain region of the first drive transistor, and forming a second contact hole in another first impurity region serving as the drain region of the second drive transistor;
• forming a conductive layer on the insulation layer and in the first and the second contact holes;
• forming a plurality of second impurity regions in a portion of the conductive layer for serving as source region and drain region of a first and second load transistor;
• patterning the conductive layer, for forming a first active layer of the first load transistor and a second active layer of the second load transistor;
• forming a trench having at least four walls including a first wall, a second wall, a third wall and a fourth wall, by etching a portion of the first and the second active layers and the semiconductor substrate to a predetermined depth of the first semiconductor substrate, wherein the plurality of first impurity regions are exposed at the four walls of the trench, and the plurality of second impurity regions are respectively exposed at a side surface of the first and the second active layers;
• forming a first gate oxide film on the first wall of the trench and a side surface of the first active layer, and forming a second gate oxide film on the third wall of the trench and a side surface of the second active layer;
• forming a first gate electrode common to the first drive transistor and the first load transistor on the first gate oxide film and forming a second gate electrode common to the second drive transistor and the second load transistor on the second gate oxide film;
• forming a third gate oxide film on the second wall and the fourth wall of the trench;
• and
• forming a gate electrode of the first and the second access transistors on the third gate oxide film.