US 6,713,343 B2 · Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric

Abstract

An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Claims28

Dependent claims

A process of manufacturing a semiconductor device, comprising:

(a) forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of said semiconductor substrate, wherein each of said first and second MISFETs has a gate electrode, and source and drain regions on a main surface of a semiconductor substrate;
(b) forming silicide layers having a metal with high melting point over said source and drain regions of said second MISFET;
(c) forming a first insulating film over said first and second MISFETs;
(d) forming a second insulating film greater than said first insulating film in film thickness over said first insulating film;
(e) forming a through hole in said second insulating film, said through hole located on the first MISFET and exposing said surface of said first insulating film;
(f) forming a first metal film oriented in a (002) plane over inner walls of said through hole and over said surface of said first insulating film in said through hole,
(g) depositing a tantalum oxide film over said first metal film;
(h) thermally treating said tantalum oxide film so as to form a polycrystalline dielectric film;
and
(i) forming a second metal film over the dielectric film.

7 more elements

A process of manufacturing a semiconductor device, comprising:

(a) forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of said semiconductor substrate, wherein each of said first and second MISFETs has a gate electrode, and source and drain regions on a main surface of a semiconductor substrate;
(b) forming silicide layers having a metal with high melting point over said source and drain regions of said second MISFET;
(c) forming a first insulating film over said first and second MISFETs;
(d) forming a first metal film oriented in a (002) plane over said first insulating film;
(e) depositing a tantalum oxide film over said first metal film;
(f) thermally treating said tantalum oxide film so as to form a polycrystalline dielectric film;
and
(g) forming a second metal film over said dielectric film.

5 more elements

A process of manufacturing a semiconductor device, comprising:

(a) forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of said semiconductor substrate, wherein each of said first and second MISFETs has a gate electrode, and source and drain regions on a main surface of a semiconductor substrate;
(b) forming a first insulating film over said first and second MISFETs;
(c) forming a connection hole for connecting distributing wires formed over said first insulating film, to said source and drain regions of said second MISFET;
(d) depositing a plurality of conductive films into said connection hole;
(e) thermally treating said plurality of conductive films for forming silicide layers over surfaces of said source and drain regions of said second MISFET;
(f) forming a second insulating film over said first insulating film in order to cover said wires;
(g) forming a third insulating film greater than said second insulating film in film thickness over said first or second insulating film;
(h) forming a hole in said third insulating film, said hole located on the first MISFET and exposing the surface of said second insulating film;
(i) forming a first metal film oriented in a (002) plane over inner walls of said hole and over said surface of said second insulating film in said hole;
(j) depositing a tantalum oxide film over said first metal film;
(k) thermally treating said tantalum oxide film so as to form a polycrystalline dielectric film;
and
(l) forming a second metal film over the dielectric film.

10 more elements

A process of manufacturing a semiconductor device, comprising:

(a) forming a first MISFET over a first region of a semiconductor substrate and a second MISFET over a second region of said semiconductor substrate, wherein each of said first and second MISFETs has a gate electrode, and source and drain regions on a main surface of a semiconductor substrate;
(b) forming a first insulating film over said first and second MISFETs;
(c) forming a connection hole for connecting distributing wires formed over said first insulating film, to said source and drain regions of said second MISFET;
(d) depositing a plurality of conductive films into said connection hole;
(e) thermally treating said plurality of conductive films for forming silicide layers over surfaces of said source and drain regions of said second MISFET;
(f) forming a second insulating film greater than said first insulating film in film thickness over said first insulating film, in order to cover said wires;
(g) forming a first metal film oriented in a (002) plane over said second insulating film;
(h) depositing a tantalum oxide film over said first metal film;
(i) thermally treating said tantalum oxide film so as to form a polycrystalline dielectric film;
and
(j) forming a second metal film over said dielectric film.

8 more elements

Dependencies are inferred from the claim text.

Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric

Life of this patent

Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric

Life of this patent

Abstract

Claims28