US 6,713,342 B2Granted

FeRAM sidewall diffusion barrier etch

AssigneesTexas Instruments Incorporated, Agilent Technologies, Inc.

InventorsFrancis G. Celii, Scott R. Summerfelt, Tomoyuki Sakoda, Chiu Chi

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Abstract

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Claims25

Dependent claims

A method of forming an FeRAM integrated circuit, comprising:

forming a transistor in a semiconductor substrate;
forming an interlayer dielectric layer over the transistor;
forming a conductive contact in the dielectric layer down to a portion of the transistor;
forming a bottom electrode diffusion barrier layer over the interlayer dielectric layer;
forming a bottom electrode layer, a ferroelectric dielectric layer, a top electrode layer, and a hard mask over the bottom electrode diffusion barrier layer;
patterning the hard mask layer;
selectively etching the top electrode layer, the ferroelectric dielectric layer, and the bottom electrode layer using the hard mask to define a capacitor stack, and exposing a portion of the bottom electrode diffusion barrier layer not covered by the capacitor stack;
forming a sidewall diffusion barrier layer over the capacitor stack and sidewalls associated therewith, and over the exposed portion of the bottom electrode diffusion barrier layer;
etching the sidewall diffusion barrier layer, thereby removing substantially all of the sidewall diffusion barrier layer over the capacitor stack and the exposed portion of the bottom electrode diffusion barrier layer while leaving at least a portion of the sidewall diffusion barrier layer over the sidewalls of the capacitor stack;
and
etching the exposed portion of the bottom electrode diffusion barrier layer.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/282,759Filed 29 Oct 2002 · us provisional application
Priority: 31 Dec 2001
Published: US 2003/0129847 A110 Jul 2003
Granted: 30 Mar 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10P 50/285
By chemical means: of materials not containing Si, e.g. PZT or Al2O3
H10B 53/00
Ferroelectric ram [feram] devices comprising ferroelectric memory capacitors
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
H10D 1/682
Capacitors having no potential barriers: having dielectrics comprising perovskite structures