Method of self-aligning a damascene gate structure to isolation regions

A method of fabricating a complimentary metal oxide semiconductor (CMOS), device on a semiconductor substrate, wherein a gate structure is defined self-aligned to isolation regions without the use of photolithographic processing, comprising the steps of:

• forming a P well region in a first portion of said semiconductor substrate to be used to accommodate an N channel metal oxide semiconductor (NMOS), device of said CMOS device;
• forming an N well region in a second portion of said semiconductor substrate to be used to accommodate a P channel metal oxide semiconductor (PMOS), device of said CMOS device;
• forming composite insulator structures on a top surface of said semiconductor substrate, each comprised with an overlying silicon nitride shape and with an underlying silicon dioxide shape;
• forming N type heavily doped source/drain regions in portions of said P well region not covered by said composite insulator structures;
• forming P type heavily doped source/drain regions in portions of said N well region not covered by said composite insulator structures;
• forming silicon oxide spacers on sides of said composite insulator structures, with each silicon oxide spacer overlying and covering a portion of a heavily doped source/drain region;
• defining shallow trench openings in portions of said semiconductor substrate not covered by said composite insulator structures or by said silicon oxide spacers;
• filling said shallow trench openings with a silicon oxide layer resulting in shallow trench isolation (STI) regions, with each STI region comprised of a silicon oxide filled shallow trench opening, and comprised of an overlying silicon oxide shape located between said composite insulator spacers, and with silicon oxide spacers previously located on sides of said composite insulator structures, now located on sides of, and a component of said overlying silicon oxide shape;
• selectively removing said composite insulator structures;
• forming silicon nitride spacers on sides of said STI regions;
• forming a high dielectric constant (high k) gate insulator layer on portions of said semiconductor substrate not covered by said STI regions or by said silicon nitride spacers;
• forming a conductive gate structure on each high k gate insulator layer with said conductive gate structure self-aligned to said STI regions;
• removing said silicon nitride spacers;
• forming N type lightly doped source/drain regions in portions of said P well region exposed by removal of said silicon nitride spacers, with each N type lightly doped source/drain region located adjacent to, and butting to an N type heavily doped source/drain region, which in turn is located underlying an STI region;
• forming P type lightly doped source/drain regions in portions of said N well region exposed by removal of said silicon nitride spacers, with each P type lightly doped source/drain region located adjacent to, and butting to a P type heavily doped source/drain region, which in turn is located underlying an STI region;
• forming a composite insulator layer comprised of an overlying silicon oxide layer and an underlying silicon nitride layer, in spaces between said STI region and said conductive gate structure, with said composite insulator layer overlying lightly doped source drain regions;
• depositing an interlevel dielectric (ILD) layer;
• forming openings in said ILD layer and in said STI regions to expose portions of said N type heavily doped source/drain regions, and to expose portions of said P type heavily doped source/drain regions;
• forming cobalt silicide layers on exposed portions of heavily doped source/drain region;
• and
• forming metal structures in said openings, with said metal structures located overlying and contacting said cobalt silicide layers.