Inverter made of complementary p and n channel transistors using a single directly-deposited microcrystalline silicon film
AssigneeThe Trustees of Princeton University
InventorsSigurd Wagner, Yu Chen
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Abstract
A p channel thin-film transistor (TFT) made of directly deposited microcrystalline silicon (uc-Si). The p TFT is integrated with its n channel counterpart on a single uc-Si film, to form a complementary metal-silicon oxide-silicon (CMOS) inverter of deposited uc-Si. The uc-Si channel material can be grown at lower temperatures by plasma-enhanced chemical vapor deposition in a process similar to the deposition. The p and n channels share the same uc-Si layer. The Figure shows the processing steps of manufacturing the TFT, where (12) represents the uc-Si layer of the device.
Claims19
A method of manufacturing a CMOS inverter comprising:
- providing a substrate;
- growing i μc-Si layer on the substrate;
- growing p+ μc-Si on the i μc-Si layer;
- patterning the p+ μc-Si source and drain for p channel TFT;
- depositing isolation SiO2 over the p channel TFT;
- forming a window in the isolation SiO2;
- depositing an n+ μc-Si layer on the i μc-Si layer through the window;
- patterning the n+ μc-Si source and drain for n channel TFT;
- removing the isolation SiO2 layer;
- defining an i μc-Si island;
- depositing SiO2 as a gate insulator;, patterning the SiO2 gate;
- opening contact holes to the n and p channel TFT source and drain;
- and
- evaporating and patterning metal to form gate source and drain electrodes of the n and p channel TFTs, and metal interconnects between the gates.
A method of manufacturing a CMOS inverter comprising:
- providing a substrate;
- growing i μc-Si layer on the substrate;
- growing n+ μc-Si on the i μc-Si layer;
- patterning the n+ μc-Si source and drain for n channel TFT;
- depositing isolation SiO2 over the n channel TFT;
- forming a window in the isolation SiO2;
- depositing an p+ μc-Si layer on the i μc-Si layer through the window;
- patterning the p+ μc-Si source and drain for p channel TFT;
- removing the isolation SiO2 layer;
- defining an i μc-Si island;
- depositing SiO2 as a gate insulator;
- patterning the SiO2 gate;
- opening contact holes to the n and p channel TFT source and drain;
- and
- evaporating and patterning metal to form gate source and drain electrodes of the n and p channel TFTs, and metal interconnects between the gates.
A method of manufacturing a CMOS inverter comprising:
- providing a substrate;
- growing i μc-Si layer on the substrate;
- growing and patterning one of a p+ or n+ μc-Si on the i μc-Si layer;
- depositing and patterning the other of an n+ or p+ μc-Si on the i μc-Si layer;
- depositing SiO2 as a gate insulator;
- patterning the SiO2 gate;
- opening contact holes in n and p channel TFT source and drain;
- and
- evaporating and patterning metal to form gate source and drain electrodes of the n and p channel TFTs and metal interconnects between the gates.
A complementary metal-silicon oxide-silicon (CMOS) inverter comprising:
- a substrate;
- a microcrystalline silicon (μc-Si) layer on the substrate;
- a p channel thin film transistor (TFT) on the μc-Si film;
- an n channel TFT on the μc-Si film;
- a patterned gate insulator on the n and p channel TFTs;
- and
- metal gate source and drain electrodes interconnected with the n and p channel TFTs.
Dependencies are inferred from the claim text.