Back to results
US 6,713,231 B1Granted
Method of manufacturing semiconductor integrated circuit devices
AssigneeRenesas Technology Corp.
InventorsNorio Hasegawa, Akira Imai, Katsuya Hayano
Life of this patent
Estimating the term…
Abstract
To alleviate the absolute value control accuracy of phases in a mask having a groove shifter structure, transfer regions 4C, 4D formed at different planar positions on the same plane of the same mask 2 are subjected to a multiple exposure by scanning exposure. Although identical mask patterns are formed over the transfer regions 4C, 4D, respective groove shifters 2d provided to these mask patterns are arranged opposite from each other.
Claims27
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) exposing a first phase shift mask pattern including a substrate groove shifter on a first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, the first phase shift mask pattern having phase errors or random defects, and
- (d) after the step (c), exposing a second phase shift mask pattern formed over the same main surface of the same mask substrate as the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, the second phase shift mask including a substrate groove shifter, and having phase errors or random defects, and a phase thereof inverted from a phase of the first phase shift mask pattern.
1 more element
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a first main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) exposing a first phase shift mask pattern including an on-substrate thin film groove shifter to a first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, the first phase shift mask pattern having phase errors or random defects, and
- (d) after the step (c), exposing a second phase shift mask pattern formed over the same main surface of the same mask substrate as the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, the second phase shift mask pattern including an on-substrate thin film groove shifter, and having phase errors or random defects, and a phase thereof inverted from a phase of the first phase shift mask pattern.
1 more element
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) exposing a first phase shift mask pattern having phase errors or random defects on a first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, and
- (d) after the step (c), exposing a second phase shift mask pattern formed over the same main surface of the same mask substrate as the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet, the second phase shift mask pattern having phase errors or random defects, and a phase thereof inverted from a phase of the first phase shift mask pattern.
1 more element
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) exposing a first phase shift mask pattern including a fine eaves type groove shifter on a first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, the first phase shift mask pattern having phase errors or random defects, and
- (d) after the step (c), exposing a second phase shift mask pattern including a fine eaves type groove shifter on the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, the second phase shift mask patter having phase errors or random defects, and having a phase thereof inverted from a phase of the first phase shift mask pattern.
1 more element
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) exposing a first phase shift mask pattern having phase errors or random defects on a first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light,
- (d) after the step (c), exposing a second phase shift mask pattern having phase errors or random defects and having a phase thereof inverted from a phase of the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light,
- (e) after the step (c), exposing again the first phase shift mask pattern to the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, and
- (f) after the step (d), exposing again the second phase shift mask pattern to the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light.
3 more elements
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) exposing a first phase shift mask pattern including an auxiliary pattern and having phase errors or random defects, on a first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light, and
- (d) after the step (c), exposing a second phase shift mask pattern including an auxiliary pattern, having phase errors and random defects and having a phase thereof inverted from a phase of the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage by reduction projection exposure using ultraviolet light.
1 more element
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) performing a scanning exposure of a first phase shift mask pattern including a groove shifter and having phase errors or random defects, on a first region of the main surface of the wafer mounted on the wafer stage using ultraviolet light as an exposure light by reduction projection, and
- (d) after the step (c), performing a scanning exposure of a second phase shift mask pattern including a groove shifter, having phase errors or random defects and having a phase thereof inverted from a phase of the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage using ultraviolet light as an exposure light by reduction projection.
1 more element
A method of manufacturing semiconductor integrated circuit devices comprising the steps of:
- (a) forming a photoresist film on a main surface of a wafer,
- (b) mounting the wafer provided with the photoresist film on a wafer stage of an exposure apparatus,
- (c) performing a scanning exposure of a first phase shift mask pattern having phase errors or random defects, on a first region of the main surface of the wafer mounted on the wafer stage using ultraviolet light as an exposure light by reduction projection, and
- (d) after the step (c), performing a scanning exposure of a second phase shift mask pattern having phase errors or random defects and having a phase thereof inverted from a phase of the first phase shift mask pattern, on the first region of the main surface of the wafer mounted on the wafer stage using ultraviolet light as an exposure light by reduction projection.
1 more element
Dependencies are inferred from the claim text.