US 6,711,665 B1 · Associative processor

Abstract

An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays. The tags logic block supports operations such as logical combinations of match result signals from the CAM cell arrays and the contents of one of the tags registers, with storage of the results in the same tags register or in a different tags register; and also concatenation of two tags registers, with a shift operation applied to the concatenated tags registers resulting in a partial transfer of the contents of one tags register to the other tags register.

Claims19

Dependent claims

An associative processor comprising:

(a) a plurality of arrays of content addressable memory (CAM) cells, each said array including a like plurality of rows of said CAM cells;
(b) at least one tag register, including a plurality of tag register cells equal in number to said rows of each said array;
and
(c) a mechanism for reversibly associating each said at least one tags register operationally with at least one of said arrays, each said tag register cell of said each tags register being associated with a respective row of each said at least one array,
wherein, for each said array, all of said rows include a like number of said CAM cells, there then being, in each said array, a number of columns of said CAM cells that is equal to said number of CAM cells in each said row, with each said row having a single said CAM cell in each said column, the associative processor further comprising:
(d) a mask register for designating at least one of said columns as an active column;
and
(e) a pattern register for storing at least one bit to be processed by a respective said active column.

5 more elements

A method of processing data, comprising the steps of:

(a) providing an associative array processor including:
(i) two arrays of content addressable (CAM) cells, each said array including a like plurality of rows of said CAM cells, and
(ii) two tags registers, each said tags register including a plurality of tag register cells equal in number to said rows;
(b) associating a first of said tags registers with a first of said arrays;
(c) associating a second of said tags registers with a second of said arrays;
(d) storing a first portion of the data in at least one of said CAM cells of said first array;
(e) storing a second portion of the data in at least one of said CAM cells of said second array;
(f) executing a first operation on each of said at least one CAM cell of said first array wherein said first portion of the data is stored, thereby loading a respective tags register bit into each said tag register cell of said first tags register that corresponds to a respective row of said at least one CAM cell of said first array wherein said first portion of the data is stored;
(g) executing a second operation on each of said at least one CAM cell of said second array wherein said second portion of the data is stored, thereby loading a respective tags register bit into each said tag register cell of said second tags register that corresponds to a respective row of said at least one CAM cell of said second array wherein said second portion of the data is stored;
and
(h) shifting said tags register bits within said tags registers, at least one of said tags register bits of said first tags register being shifted to said second tags register.

8 more elements

Dependencies are inferred from the claim text.

Associative processor

Life of this patent

Associative processor

Life of this patent

Abstract

Claims19