Phase locked loop employing a fractional frequency synthesizer as a variable oscillator
AssigneeWestern Digital Technologies, Inc.
InventorRobert L. Cloke
Life of this patent
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Abstract
A phase locked loop (PLL) circuit is disclosed comprising a phase detector for generating a phase error between an input oscillating signal and an output oscillating signal. A fractional frequency synthesizer (FFS) generates the output oscillating signal in response to the phase error, wherein the FFS comprises an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr. The variable I is an integer value, and the variable Fr is a fractional value, both of which are generated in response to the phase error.
Claims31
A phase locked loop (PLL) circuit comprising:
- (a) an input for receiving an input oscillating signal;
- (b) an output for outputting an output oscillating signal;
- (c) a first phase detector for generating a first phase error between the input oscillating signal and the output oscillating signal;
- and
- (d) a fractional frequency synthesizer (FFS) for generating the output oscillating signal in response to the first phase error, the FFS comprising an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr,
- wherein:
- I is an integer value;
- Fr is a fractional value;
- and
- the variables I and Fr are generated in response to the first phase error.
A method of frequency locking an output oscillating signal to an input oscillating signal, the method comprising the steps of:
- (a) generating a first phase error between the input oscillating signal and the output oscillating signal;
- (b) generating variables I and Fr in response to the first phase error, where I is an integer value and Fr is a fractional value;
- and
- (c) dividing a frequency of a selected oscillating signal by (I+Fr).
A self-servo writing disk drive comprising:
- (a) a disk comprising a plurality of concentric tracks;
- (b) a head connected to a distal end of an actuator arm, wherein:
- the head for servo-writing a plurality of the tracks by writing embedded servo sectors at a predetermined interval around the circumference of the disk;
- and
- the head for reading a first write clock from a previously servo-written track, the first write clock for writing the embedded servo sectors and a second write clock to a subsequent track;
- (c) a preamp circuit for generating a write signal applied to the head for writing the embedded servo sectors and the second write clock to the subsequent track;
- and
- (d) a phase locked loop (PLL) for generating a clock signal for use in writing the embedded servo sectors and the second write clock to the subsequent track, the PLL comprising:
- an input for receiving an input oscillating signal representing the first write clock,
- an output for outputting an output oscillating signal used to generate the clock signal;
- a first phase detector for generating a first phase error between the input oscillating signal and the output oscillating signal;
- and
- a fractional frequency synthesizer (FFS) for generating the output oscillating signal in response to the first phase error, the FFS comprising an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr,
- wherein:
- I is an integer;
- Fr is a fractional value;
- and
- the variables I and Fr are generated in response to the first phase error.
Dependencies are inferred from the claim text.